1Executive Summary
Research statusNEURO-SYNAPSE-OMNI is a proposed R&D architecture, not a fabricated or measured device. The references currently listed provide general memristor background but no experimental Ho₂S₃:Sc device data. Unless linked to a material-specific source, numerical performance values below are design targets or hypotheses.
Scientific improvement
This means new, reproducible knowledge: an attributed mechanism, a composition–structure–property relationship, a predictive model, a measurement method, or a better-established physical limit. A more complex composition is not automatically a scientific improvement.
Computing improvement
This means a measured task-level gain in accuracy, latency, throughput, energy, memory traffic, usable density, robustness, or calibration time. Converters, controllers, communication, errors, and fallback solutions must be included.
2Six Atomic-Scale Design Hypotheses
Each element of the (Ag,Li)-Te / (Ho,Sc,Ca)₂(S,F)₃ stack has a proposed role to test. These assignments are experimental variables, not measured material properties; the sections below define the controls needed to accept or reject them.
⚡
Co-Ionic Dynamics Hypothesis (Ag⁺ / Li⁺)
The design tests whether Ag can support a relatively fast, volatile ECM response while Li produces a slower, retained host-composition change. The timescales, mechanisms, retention, and 10-bit target must be measured independently.
🧲
Forming-Free Hypothesis (Calcium)
Aliovalent Ca²⁺ substitution on Ho³⁺ sites can be compensated by F⁻ substitution and/or anion vacancies. Whether this produces a forming-free path at 0.2 V must be established against undoped and Ca-only control cells.
☢️
Radiation & Cryogenic Hypothesis (Fluorine)
Fluorine may passivate defects in the sulfide lattice, but radiation tolerance and ionic mobility at 4 K require irradiation, spectroscopy, and temperature-dependent transport measurements.
🎯
Filament-Bias Hypothesis (Scandium)
The 17.3% six-coordinate reference-radius mismatch motivates testing whether Sc³⁺ perturbs local strain or defect energies. It predicts neither the sign of the energy change nor a preferred filament. Ordered Sc rows and separate cycle-to-cycle and device-to-device CV(VSET) = σ/μ < 2% targets are unmeasured program objectives.
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Foundry-Integration Candidate (Tellurium)
Ag–Te and Cu–Te phases may buffer active-metal release relative to a pure metal source. SIMS depth profiles, barrier tests, anneals, and foundry contamination review must show whether Ag or Cu diffusion remains within an acceptable process envelope.
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Host-Matrix Candidate (Ho₂S₃)
Known Ho₂S₃ phases motivate investigation as a rare-earth sulfide host. Film phase, transport pathways, bandgap, low-temperature deposition, air stability, and BEOL compatibility all require direct characterization.
Six system-enabling innovations
Ion-selective interface pair
A thin blocking or exchange layer is proposed on each side of the adaptive host so Ag and Li do not see the same injection barrier. The innovation is useful only if isotope/depth profiles show separable fluxes and the added resistance does not erase the energy advantage. Fallback: place fast and retained states in two cells.
Differential reference synapse
Pair an active cell with a composition-matched, ion-blocked reference. Differential readout can reject temperature, contact, humidity, and common-mode drift while exposing chemistry-specific change. Fallback: use reference rows and periodic digital calibration.
Charge-budgeted learning pulse
Program by measured delivered charge rather than voltage width alone. Real-time current integration terminates a pulse before filament overgrowth and makes Ag, Li, and control cells comparable. Fallback: 1T1R compliance plus verify-write.
Replaceable G24 transducer tile
Keep ionic memory, G23 Bi₂Te₃ spin conversion, G9 optical modulation, and harvesting on separately qualified dies joined by low-loss bonding. A failed material module can then be replaced without invalidating the memory. Fallback: electrical G21 with external photonic or magnetic I/O.
CommercialStack modular partition
Combine a TiN/HfOx memory plane, NbO2 selector, Cu interconnect, Al2O3/SiO2 barriers and a separately qualified ITO/ZnO sensor tile. The claim is manufacturability by decomposition into known process families, not demonstrated compatibility or performance.
DieuModeStack qualification firewall
Keep diamond-NV, graphene, carbyne, h-BN, Au, Os, isotopically enriched Si-28 and TaN/TaC in separately replaceable coupons or bonded modules. Scientific coherence requires an explicit transduction path and matched controls; material superlatives alone create no processor advantage.
How to read an innovation claimAsk three questions: what state variable changes, which control removes the simpler explanation, and what measured system metric improves after peripheral cost. A novel composition without those three answers is a research variable, not yet an innovation.
Ag
Silver
Fast-STP source candidate
Li
Lithium
Retained-insertion candidate
Te
Tellurium
Ion-buffer candidate
Ho
Holmium
Candidate host-matrix cation
Sc
Scandium
Filament-bias candidate
Ca
Calcium
Forming-control candidate
S
Sulfur
Candidate anion-defect pathway
F
Fluorine
Passivation candidate
Er
Erbium
G24 optical-emitter candidate
Bi
Bismuth
G23 Bi₂Te₃ interface constituent
2CCommercial Processor
Supplemental premium module outside G1–G24CommercialStack is a decision architecture assembled from established material families. It is not a fabricated processor, a foundry-approved flow or a claim that all listed interfaces are mutually qualified.
Reference composition: TiN / HfOx / NbO2 / Cu / Al2O3 / SiO2 / ITO / ZnO. The scientifically defensible implementation is modular: HfOx stores the electrical state, NbO2 is evaluated as a selector, TiN and Cu provide qualified electrode/interconnect functions, Al2O3/SiO2 provide barriers and isolation, and ITO/ZnO remains a separately qualified optical-input tile.
Commercial scientific contribution
Produce a reproducible process–structure–function reference for HfOx, the NbO2 selector, and their BEOL interfaces. This baseline allows advanced-stack differences to be attributed rather than compared with an assumption.
Commercial computing contribution
Test in-memory computing, nonvolatile calibration, and near-sensor filtering in an industrializable chain. Progress is validated through energy–delay–accuracy, avoided traffic, yield, and availability against MCU/NPU baselines.
Optical input tileBonded ITO/ZnO sensor or modulator; removable if optical benefit is not demonstrated.
IsolationSiO2 dielectric and patterned Al2O3 diffusion/passivation barrier.
Memory + selectorTiN/HfOx VCM cell paired with a separately optimized NbO2 threshold selector.
BEOL routingCu interconnect with qualified TiN barrier/electrode interfaces and conventional CMOS control below.
Commercial qualification logic
| Module | Why it is realistic | Unresolved integration risk | Required exit gate | Fallback |
|---|---|---|---|---|
| TiN/HfOx memory | Strong semiconductor process precedent, scalable deposition and existing device-model ecosystem. | Local forming, drift, oxygen exchange, analog variability and electrode dependence. | Full device distributions for endurance, retention, update quality, yield and energy. | Binary HfOx 1T1R with verify-write. |
| NbO2 selector | Documented threshold-switching research base and direct relevance to dense crossbar access. | Phase control, hold current, leakage, self-heating, endurance and thermal cross-talk. | Array margin and task energy beat 1R and 1T1R controls after selector overhead. | VO2 comparator or transistor-selected array. |
| Cu/TiN routing | Mature interconnect and diffusion-barrier process families. | An intentionally active Cu path is not equivalent to sealed Cu wiring; diffusion and contamination remain flow-specific. | SIMS/TEM diffusion bounds, contact resistance, electromigration and thermal-budget qualification. | W or isolated Cu companion die. |
| Al2O3/SiO2 isolation | Widely used dielectric and passivation families with scalable deposition options. | Pinholes, stress, plasma damage and excessive blocking of the state-changing species. | Environmental gain without loss of switching window, yield or energy. | Thinner local barrier, SiN alternative or package-level passivation. |
| ITO/ZnO optical input | Established transparent-conductor and oxide-semiconductor materials with known optical characterization methods. | Indium supply, sputter damage, oxygen-vacancy drift, optical loss and bonded alignment. | Measured optical-to-decision benefit over an external sensor plus electrical processor. | Commercial photodiode or image sensor connected to the electrical tile. |
CommercialStack invention portfolio
Predictive-maintenance edge module
Fuse vibration or acoustic events with local HfOx weights to output an anomaly score without streaming every raw sample. Required proof: task accuracy, drift, latency and complete module energy versus an MCU/NPU baseline.
Transparent event-vision gateway
Bond the ITO/ZnO tile above an electrical memory array to prefilter motion or illumination changes near the sensor plane. Required proof: optical loss and alignment must be offset by lower data movement or a unique sensing function.
Adaptive power-electronics calibrator
Retain converter, motor or battery-sensor correction parameters close to a conventional controller while the CPU preserves deterministic safety logic. Required proof: stability and fault behavior across temperature, ageing and power cycles.
Wearable biosignal research prefilter
Perform bounded ECG, EMG or inertial-event denoising before digital classification. This is a research instrument concept, not a medical-device claim; subject-level validation, safety, privacy and regulatory planning remain mandatory.
Why CommercialStack is realisticIts realism comes from process familiarity, modular partitioning and available control structures, not from assuming compatibility. Every high-risk interface can be tested against a conventional substitute, and the optical tile can be removed without invalidating the HfOx processor core.
2EDieuModeStack Research Processor
Theoretical supplemental premium module outside G1–G24DieuModeStack is a falsifiable heterogeneous research architecture, not a performance forecast. “Perfect graphene,” extended defect-free carbyne and a complete compatible process flow are idealized boundary conditions rather than available production specifications.
Reference composition: NV-doped diamond / ideal graphene / carbyne / h-BN / Au / Os / isotopically enriched Si-28 / TaN or TaC. Scientific coherence requires these materials to remain separately qualified sensing, transport, barrier, contact and control modules. Their coexistence does not imply superconductivity, zero loss, unlimited lifetime, quantum advantage or superior AI performance.
DieuModeStack scientific contribution
Explore limits in coherence, noise, 2D transport, tunnelling, contacts, and transduction using separate coupons. Progress means a new property measured with uncertainty, not an assembly of rare materials.
DieuModeStack computing contribution
Target optical, magnetic, or quantum information unavailable to the electrical stack, then process it locally. Without a unique function or source-to-decision gain, the module is removed rather than presented as an accelerator.
Rarity and cost boundaryThis material is extremely rare, expensive, or difficult to produce. It is included only in DieuModeStack. This statement applies individually to every extreme material listed in the audit below.
Quantum/sensor surfaceNV-doped diamond coupon with optical and microwave readout isolated from the memory core.
2D transport interfaceGraphene/h-BN heterostructure with bounded carbyne test structures; no assumption of perfect transfer or infinite chains.
Contacts and barriersAu and Os research contacts with TaN/TaC refractory diffusion barriers; each contact pair requires a conventional control.
Control substrateIsotopically enriched Si-28 control die used only where spin coherence or isotope disorder is an explicit measured variable.
Extreme-material audit
| Material | Bounded scientific role | Primary limitation | Minimum evidence before integration | Rarity / cost decision |
|---|---|---|---|---|
| NV-doped diamond | Optically addressable defect-spin sensing or transduction coupon. | Controlled NV density, charge state, surface noise, optical collection and wafer-scale fabrication. | Spin/optical signal, coherence under the actual interface and measured transduction energy. | DieuModeStack only; defect-controlled material and processing are exceptionally demanding. |
| Ideal graphene | High-mobility two-dimensional channel, transparent electrode or local sensor. | Real graphene has defects, grain boundaries, residues, contact resistance and substrate-induced disorder. | Mobility, noise, contact resistance, uniformity and ageing after complete transfer and patterning. | DieuModeStack only when electronic-grade area and interfaces exceed conventional controls. |
| Carbyne | Bounded one-dimensional transport or electromechanical test structure. | Long free-standing chains are chemically and mechanically unstable and difficult to contact reproducibly. | Verified chain structure and length, stability, contact physics and repeated device statistics. | DieuModeStack exploratory coupon only; not a production interconnect assumption. |
| h-BN | Atomically thin dielectric, tunnel barrier or encapsulation layer for a 2D interface. | Thickness uniformity, defects, transfer contamination, pinholes and scalable growth. | Breakdown, leakage, trap density, interface cleanliness and wafer-level yield. | DieuModeStack only; conventional dielectric fallback remains mandatory. |
| Au | Low-oxidation laboratory contact and optical/plasmonic reference. | Cost, adhesion, diffusion and incompatibility with mainstream silicon contamination rules. | Contact resistance, diffusion bounds, ageing and benefit over TiN/Cu/Pt controls. | DieuModeStack bonded module only unless a unique measured function requires Au. |
| Osmium | Dense high-atomic-number contact or spin-orbit research comparator. | Scarcity, nonstandard processing and severe hazard if volatile OsO4 forms. | Closed-process EHS review, phase/oxidation control, contact data and unique benefit over safer metals. | DieuModeStack only; exclude if oxidation containment and recovery are not demonstrated. |
| Isotopically enriched Si-28 | Low-nuclear-spin control substrate for experiments where isotope disorder limits coherence. | Enrichment cost and no automatic advantage for ordinary room-temperature logic or memory. | Matched natural-Si control showing that isotopic composition improves the named system metric. | DieuModeStack only when isotope sensitivity is directly measured. |
| TaN / TaC | Refractory electrode, diffusion barrier or mechanically robust contact layer. | Stoichiometry, stress, etch complexity, interface reactions and high-temperature process interactions. | Phase, resistivity, adhesion, diffusion blocking, stress and thermal-budget data. | DieuModeStack qualified barrier; retain TiN/W as industrial controls. |
DieuModeStack invention portfolio
NV-diamond adaptive magnetometry head
Couple an NV sensing coupon to a conventional or CommercialStack memory tile for local drift correction and event compression. Required proof: calibrated field sensitivity, optical/microwave overhead and no degradation from the bonded interface.
Quantum-experiment calibration cache
Use an enriched Si-28 control die only where isotope disorder is shown to limit a measured coherence or calibration function. The quantum processor, qubits and error correction remain external; natural-silicon and CMOS controls are mandatory.
Graphene/h-BN low-signal interface analyzer
Use a separately contacted 2D heterostructure to study charge, tunnelling or surface events, with local adaptive filtering on another die. Required proof: post-transfer mobility, noise, contact stability and advantage over mature sensor interfaces.
Extreme-interface discovery platform
Compare bounded carbyne structures, Au/Os contacts and TaN/TaC barriers as replaceable test coupons rather than a production processor. The invention is the controlled modular assay; any material without a unique measured signal is removed.
CommercialStack vs PremiumStack vs DieuModeStack
| Decision axis | CommercialStack | PremiumStack | DieuModeStack |
|---|---|---|---|
| Core composition | TiN/HfOx/NbO2/Cu with Al2O3/SiO2 isolation and optional ITO/ZnO tile. | Selected G12–G24 Ag/Li/Te, fluorosulfide, optical and spin modules after independent qualification. | NV-diamond, graphene, carbyne, h-BN, Au, Os, enriched Si-28 and TaN/TaC modules. |
| Scientific status | Credible engineering integration program using established material families. | Exploratory differentiated-material program with several unverified device mechanisms. | Theoretical heterogeneous research program with idealized and exceptionally difficult components. |
| Manufacturing route | CMOS/BEOL-oriented electrical core plus optional bonded optical die. | Dedicated material modules, contamination segregation and heterogeneous packaging. | Separately fabricated coupons or dies; no credible monolithic all-material flow is assumed. |
| Principal value hypothesis | Controllable oxide memory and selector integration with realistic industrial fallbacks. | Device-resident temporal dynamics, resilience and specialized transduction if measured. | Unique sensing or transport functions that survive complete interface and system accounting. |
| Dominant risk | Selector variability, interface qualification, optical alignment and array yield. | Unattributed chemistry, contamination, coupled state variables and compound yield. | Material availability, idealization, incompatible growth conditions, EHS and near-zero compound yield. |
| Decision rule | Advance after reproducible array and task benefit versus conventional controls. | Advance one module at a time only after chemically attributed benefit. | Retain only modules with an independently measured unique function; otherwise revert to CommercialStack. |
Why DieuModeStack is theoretical but scientifically coherentEach material has a bounded, testable role and an explicit conventional control. Coherence comes from modular transduction and falsifiable exit gates, not from assuming that extreme material properties survive interfaces or combine constructively. The architecture remains theoretical until separately fabricated modules show an end-to-end benefit.
2FEnergy Comparator · CommercialStack vs PremiumStack vs DieuModeStack
Data boundaryNone of the three complete architectures has been fabricated and measured under comparable conditions. This comparator defines the budget to measure and a qualitative energy-risk ranking; it creates no pJ value, efficiency claim, or acceleration claim.
A valid comparison must use the same task, accuracy, useful throughput, activity factor, and retention duration. Cell-switching energy alone is insufficient: conversion, selection, calibration, communication, transduction, and cooling can dominate the system.
\[E_{\mathrm{task}}=N_{\mathrm{read}}E_{\mathrm{read}}+N_{\mathrm{write}}E_{\mathrm{write}}+E_{\mathrm{selection}}+E_{\mathrm{ADC/DAC}}+E_{\mathrm{calibration}}+E_{\mathrm{communication}}+E_{\mathrm{transduction}}+E_{\mathrm{cooling}}+P_{\mathrm{standby}}t\]
Complete energy budget
1 · CellIntegrate V(t)I(t) over every read, write, verify, and reset operation.
2 · ArrayAdd selectors, lines, leakage currents, IR drop, and disturbed cells.
3 · PeripheryCount drivers, ADC/DAC, CMOS control, calibration, and error correction.
4 · InterfacesCount sensors, lasers, microwaves, magnets, transducers, and data links.
5 · EnvironmentInclude standby, thermal regulation, and cooling wall power.
6 · Useful taskNormalize by correct decisions, useful events, or accepted operations.
| Energy item | CommercialStack | PremiumStack | DieuModeStack | Required common measurement |
|---|---|---|---|---|
| Memory write | Low-to-medium risk. HfOx has precedent, but forming, verify-write, and variability can multiply pulses. | Medium-to-high risk. Ag/Li/Te may target gradual updates, with possible slow-transport and stabilization costs. | Undetermined. Extreme materials do not define one common memory-writing mechanism. | \(\int V(t)I(t)dt\), pulse count, and verification count per accepted state. |
| Read and accumulation | Most credible baseline. Conventional electrical array, subject to selector and converter overhead. | Conditional gain. Local temporal states are possible, but noise, drift, and multichannel readout increase peripheral cost. | High risk. Contacts and 2D interfaces add a specialized measurement chain. | Energy per correct output at identical accuracy, array size, and frequency. |
| Selection, conversion, and calibration | Manageable. NbO2, ADC/DAC, and compensation still must be counted. | High. Multiple species, retention times, and 3D planes require more calibration. | Very high. Each coupon may require its own optical, RF, or analog interfaces. | Active and standby power for all periphery, including recalibration frequency. |
| Data communication | Reduction potential for embedded AI if weights remain near compute. | Higher but conditional potential with temporal filtering or local sensing. | Not demonstrated. Modularity may instead multiply die crossings. | Bytes moved and link energy per complete sensor-to-decision task. |
| Optical / spin transduction | Optional. The ITO/ZnO tile can be removed if it does not win. | Specialized. G9/G23 is retained only for a measured unique function. | Likely dominant. Lasers, optical collection, microwaves, and magnets must be included. | Source-to-useful-information energy, loss, noise, alignment, and detection efficiency. |
| Cryogenics and thermal control | Low at 300 K; qualification required at 40–80 K and 4 K. | High if cryogenic. Ionic mobility, local heating, and retention may impose costly cycles. | Very high or out of scope. Si-28/NV alone does not justify cryostat cost. | Heat at each stage and cryostat wall power per useful experiment. |
| Provisional energy verdict | Priority baseline. Lowest system-overhead risk for the first measurement. | Promote by function. Must offset its periphery through less traffic, better adaptation, or a new function. | Discovery platform. No presumed global advantage; each module must justify its own budget. | Compare energy–delay–accuracy, fabrication yield, and service life on the same workload. |
Decision ruleCommercialStack wins by default until a PremiumStack or DieuModeStack function reduces total task energy or provides information unavailable to the baseline. A cell-level reduction that raises conversion, calibration, or cooling energy is a system-level failure.
2GTarget Applications
Selection ruleThe recommended stack is the least complex experimental starting point capable of testing the intended value. PremiumStack and DieuModeStack replace CommercialStack only when a differentiated module passes a defined application metric.
| Application | Reference architecture | Proposed role | Advantage to demonstrate | Pass metrics | Conditional evolution |
|---|---|---|---|---|---|
| Embedded AI | CommercialStack | Local inference, event filtering, and predictive maintenance with HfOx weights near compute. | Reduce memory traffic and raw-data transmission within a constrained energy envelope. | Accuracy, latency, energy per decision, drift, availability, and battery life against MCU/NPU. | PremiumStack G19/G21 only if temporal state improves the task after calibration; G22 if 3D density survives yield loss. |
| Cryo-compute | CommercialStack G1 at 40–80 K | Calibration memory, parameter cache, and classical preprocessing at a stage warmer than the QPU. | Reduce traffic, latency, or reloading without exceeding the cryostat heat budget. | Dynamic energy, leakage, cable heat, retention, thermal cycling, noise, and wall power. | PremiumStack G16/G19 after success at 40–80 K and then 4 K; no mK placement without non-disturbance evidence. |
| Opto-compute | CommercialStack + ITO/ZnO tile | Separate optical detection or modulation with electrical memory and local adaptation. | Avoid part of the conversion or data movement, or provide a unique optical input. | Source-to-decision energy, insertion loss, bandwidth, noise, alignment, accuracy, and ageing. | PremiumStack G9/G24 if integration wins; DieuModeStack graphene/h-BN/NV only as a compared transducer. |
| Quantum support | CommercialStack G1 external to the QPU | Classical calibration memory, pulse logging, and prefiltering behind cryo-CMOS, FPGA, or RF electronics. | Improve calibration time, loop latency, or availability without claiming quantum acceleration. | Fidelity, T1/T2, error rate, jitter, heat, spectral noise, and experimental throughput versus a digital controller. | PremiumStack G19 for temporal drift; DieuModeStack NV/Si-28 only if a measurement or coherence function is directly proven. |
Product path
Start with CommercialStack embedded AI because it offers the shortest route to a complete MCU/NPU comparison. Then extend toward opto-compute or cryo-compute with one differentiated module at a time.
Scientific path
Use PremiumStack to test temporal states and DieuModeStack for unique transducers. A quantum application remains a classical support function until an effect on a QPU metric is measured.
2HScientific and Computing Improvements
Two independent axesA generation can produce a major scientific improvement without accelerating a computation, for example by isolating a mechanism. Conversely, an architecture can improve a task using known materials. This dossier validates progress only when its metric and control are explicit.
Cross-cutting contribution from G1 to G24
| Family | Target scientific improvement | Potential computing improvement | Decisive measurement | What invalidates progress |
|---|---|---|---|---|
| G1–G2 · VCM baselines | Establish a reproducible baseline linking oxygen exchange, interfaces, forming, drift, and conductance distributions. | More stable weight or calibration memory, with local readout and potentially reduced memory traffic. | Multi-lot distributions, complete energy, retention, and task accuracy against Flash/SRAM plus NPU. | The gain disappears after verify-write, ADC/DAC, error correction, or ageing. |
| G3–G4 · Cu/Ag ECM | Separate nucleation, growth, dissolution, and volatility of metal filaments under controlled charge budgets. | Fast events, physical forgetting filters, stochastic sampling, or low-voltage updates. | Transient currents, chemical profiles, temporal statistics, and event-stream benefit. | Dendrites, shorts, stochastic bias, or digital calibration cancel the advantage. |
| G5–G6 · HfOx dopants | Quantify how valence, traps, and vacancy binding change plasticity beyond undoped oxide. | More gradual analog updates and adaptive thresholds with less software compensation. | Atomic occupancy, defect spectroscopy, and multi-lot improvement against G1. | Secondary phases, leakage, or dopant variability degrade retention and yield. |
| G7–G9 · Selection and optical input | Connect threshold transitions, self-heating, and phototransport to integrated-array margins. | Denser addressing, sneak-path suppression, and optical preprocessing near the sensor. | Array margin, post-selector energy, responsivity, noise, and source-to-decision energy. | Heat, optical loss, or periphery costs more than the avoided data movement. |
| G10–G13 · Host and reservoirs | Create a Ho₂S₃ phase–defect–transport map and measure whether Ag–Te/Cu–Te actually controls ionic activity. | Wider programming window, better weight repeatability, and task-based industrial Ag/Cu selection. | Phase purity, SIMS/TEM, ionic activity, delivered charge, and G4/G3 comparison at identical geometry. | The reservoir adds drift, contamination, or resistance without improving the algorithm. |
| G14–G18 · Defects and coupled chemistry | Causally test solubility, strain, Ca/F compensation, passivation, Li insertion, and Ag/Cu mixing. | Reduced initialization, more stable weights, distributed analog state, and adjustable forgetting time. | Composition series, chemical attribution, first-cycle yield, separable levels, and endurance. | Mechanisms remain correlated, irreversible, or more costly than a calibrated simple cell. |
| G19–G21 · Temporal states | Determine whether fast and slow states are physically separable first in two cells and then in one co-ionic cell. | Local temporal memory for event sequences, online adaptation, and drift detection with less digital state. | Ag/Li/host identification, time constants, sequential accuracy, and energy–delay against a digital recurrent model. | Coupling, drift, or periphery makes G21 inferior to paired G19 or digital memory. |
| G22–G24 · System integration | Establish 3D yield and optical/spin transduction limits across measured heterogeneous interfaces. | Greater local capacity, less weight movement, and multimodal instruments that decide near the source. | Vertical yield, thermal behavior, IR drop, loss, noise, and source-to-decision energy against conventional chiplets. | No unique function or task gain remains after bonding, lasers, RF, and conversion. |
Contribution of the three supplemental architectures
CommercialStack · baseline progress
Science: turn known materials into comparable process interfaces and distributions. Computing: establish the first credible local-inference, calibration, and memory-traffic budget. Its main contribution is a falsifiable industrial baseline.
PremiumStack · functional progress
Science: attribute reservoir, dopant, and temporal-state effects. Computing: test multiscale adaptation, 3D density, and resilience. It advances only if a module beats CommercialStack on a declared metric.
DieuModeStack · exploratory progress
Science: measure extreme interfaces, sensors, and transducers under conventional controls. Computing: target new information, not presumed speed. Every coupon without a unique function is removed.
Common progress indicators
| Level | Scientific indicators | Computing indicators | Minimum control |
|---|---|---|---|
| Material | Phase, composition, defects, migration energy, mechanism, and uncertainty. | State window, noise, drift, programming energy, and thermal stability. | Undoped material, inert electrode, and independent lot. |
| Device | Causality between processing, structure, and electrical/optical/spin response. | Endurance, retention, latency, useful levels, error rate, and yield. | Previous generation at identical geometry and pulses. |
| Array | Interaction, thermal, line, selector, and spatial-variability effects. | Effective accuracy, throughput, energy, IR drop, sneak paths, and usable capacity. | 1T1R, SRAM/DRAM, or a conventional array of equal size. |
| System | Predictive model valid out of sample with documented operating limits. | Energy–delay–accuracy, traffic, availability, calibration cost, and quality of service. | CPU/GPU/NPU/FPGA or a complete sensor-to-compute chain at equal function. |
Final criterion“More scientific” means better explained and more falsifiable; “better computing” means a task executed better within its real envelope. Generation number, price, rarity, and material count do not replace this evidence.
2AG1–G24 Chemical-Property Audit
Completeness boundaryThis audit covers every chemical-property family that can control the proposed technology. It does not claim that every value is known. Where the composition, phase, defect population, reaction, or interface has not been fabricated and measured, the entry is explicitly a calculation or measurement requirement rather than a material property.
The same audit is applied to every generation: composition and phase; oxidation states and charge neutrality; native and dopant defects; ionic and electronic transport; redox and competing reactions; interfaces and band alignment; environmental and thermal stability; and the quantitative evidence needed for a decision.
| Generation | Composition, phase & solubility | Valence, defects & charge | Ion/electron transport & redox | Interfaces, bands & traps | Stability & degradation | Required quantitative closure | Status |
|---|---|---|---|---|---|---|---|
| G1 HfOx | HfOx phase and x. | Hf valence and oxygen vacancies. | VCM versus trapping. | TiN/oxide barriers. | Drift and electrode redox. | x, Ef, Em, D(T), retention. | Established family; local values required. |
| G2 Al₂O₃ interface | Bilayer thickness and intermixing. | Oxygen exchange and fixed charge. | Barrier-limited VCM. | Band offsets and interface traps. | Stress and barrier breakdown. | Offsets, trap density and oxygen flux. | Strong precedent; stack-specific. |
| G3 Cu ECM | Cu phase and electrolyte solubility. | Cu⁰/Cu⁺/Cu²⁺ balance. | Oxidation, migration and plating. | Nucleation barrier and contact potential. | Residual Cu and filament coarsening. | Cu activity, transference and D(T). | Established ECM family. |
| G4 Ag ECM | Ag phase and interfacial products. | Ag⁰/Ag⁺ and trapped charge. | Ag dissolution and plating. | Nucleation overpotential. | Dendrites, shorts and tarnishing. | Ag activity, D(T), exchange current. | Established ECM family. |
| G5 HfOx:Cr | Cr dose, site and secondary phases. | Cr valence and vacancy binding. | Trap/redox-assisted VCM. | Cr-dependent levels and leakage. | Segregation and chamber memory. | Site fraction, levels and binding. | Exploratory dopant branch. |
| G6 HfOx:Mn | Mn dose, site and secondary phases. | Mn multivalence and compensation. | Polaron/trap-assisted VCM. | Mn-dependent levels and leakage. | Valence drift and segregation. | Site fraction, levels and mobility. | Exploratory dopant branch. |
| G7 VO₂ | VO₂ stoichiometry and polymorph. | V valence and oxygen defects. | Threshold transition and heating. | Selector/cell contact resistance. | Thermal cycling and drift. | Threshold/hold distributions and enthalpy. | Selector precedent; integration open. |
| G8 NbO₂ | NbO₂ phase purity. | Nb valence and oxygen defects. | Threshold transition and heating. | Selector/cell barriers. | Self-heating and endurance. | Threshold/hold distributions and leakage. | Research selector precedent. |
| G9 ITO/ZnO | ITO/ZnO stoichiometry and texture. | O vacancies and carrier density. | Photocarrier generation/transport. | Optical/electrical contact offsets. | Indium diffusion and sputter damage. | Loss, responsivity, lifetime and offsets. | Known materials; module unqualified. |
| G10 Ho₂S₃ | Polymorph, sulfur activity and texture. | Ho³⁺ and sulfur defects. | Vacancy motion versus trapping. | Contact offsets and trap spectrum. | S loss, oxidation and moisture. | Phase window, Ef, Em, D(T). | Compound known; device unassigned. |
| G11 Encapsulation | Barrier thickness and pinholes. | Fixed charge and trapped species. | Diffusion and ion-blocking balance. | Barrier/interface traps. | Stress, moisture and delamination. | Permeability, stress and ageing rates. | Mature materials; stack-specific. |
| G12 Ag–Te | Ag–Te phases and fractions. | Ag/Te valence and defects. | Ag activity and release. | Reservoir/host offsets. | Segregation and Te loss. | Activities, D(T) and release law. | Reservoir hypothesis. |
| G13 Cu–Te | Cu–Te phases and fractions. | Cu/Te valence and defects. | Cu activity and release. | Reservoir/host offsets. | Segregation and Te loss. | Activities, D(T) and release law. | Reservoir hypothesis. |
| G14 Ho₂S₃:Sc | Sc solubility and occupancy. | Isovalent substitution and binding. | Defect-migration change. | Band and trap changes. | Clustering and sulfur loss. | Solubility, binding and D(T,x). | Exploratory series. |
| G15 Fluorosulfide | F sites, bonding and solubility. | F compensation and defect pairs. | Passivation versus ion blocking. | Dipoles, bands and traps. | F loss and reaction products. | Occupancy, binding and D(T,F). | Co-doping hypothesis. |
| G16 Ca/F host | Ca/F solubility surface. | Measured charge compensation. | Vacancy association and leakage. | Space charge and band bending. | Segregation and reactive phases. | Activities, binding and phase map. | Coupled-composition hypothesis. |
| G17 Li insertion | Li sites and metastable products. | Li⁺ and host compensation. | Insertion/extraction kinetics. | Ion-selective interface barriers. | Trapping, plating and self-discharge. | Insertion voltage, DLi and reversibility. | Device hypothesis. |
| G18 AgCu–Te | Ternary phases and segregation. | Ag/Cu/Te valence balance. | Competing metal release. | Mixed-reservoir offsets. | Phase separation and drift. | Ternary map, activities and fluxes. | Mixed-reservoir hypothesis. |
| G19 Paired Ag/Li | Each cell audited independently. | Separate charge inventories. | Independent fast/slow paths. | CMOS isolation and coupling. | Cross-talk and package ageing. | Matched kinetics and system energy. | Compound architecture. |
| G20 Au ECM | Au phase and electrolyte solubility. | Au⁰/Au⁺ where supported. | Oxidation, transport and plating. | Nucleation and adhesion barriers. | Diffusion and irreversible residue. | Direct Au flux, activity and D(T). | Exploratory active-ion branch. |
| G21 (Ag,Li)–Te | Ternary phases and host sites. | Ag/Li/host charge balance. | Coupled Ag and Li fluxes. | Ion-selective barriers and space charge. | Interference and irreversible products. | μ, transference, D(T,state), kinetics. | Complete co-ionic concept. |
| G22 3D crossbar | Every plane and via phase. | Plane-to-plane defect distributions. | Vertical diffusion and thermal coupling. | Via/cell contact maps. | Compound ageing and heat. | Vertical yield, diffusion and thermal maps. | Integration hypothesis. |
| G23 Bi₂Te₃ | Stoichiometry, texture and surface state. | Bi/Te defects and Fermi level. | Bulk/surface spin-charge transport. | Spin transparency and interface dipoles. | Oxidation and Te loss. | Carrier density, Fermi level and conversion. | Interface research module. |
| G24 Complete system | All qualified module phases. | Cross-module charge balance. | Ionic, optical and spin cross-talk. | Every bonded interface and loss. | Compound yield and package stress. | End-to-end reaction, loss and ageing map. | Frontier system hypothesis. |
Supplemental premium-architecture chemical audit
Taxonomy boundaryThe rows below audit CommercialStack, PremiumStack and DieuModeStack materials without adding generations or altering the authoritative 24-row G1–G24 audit above. Every status remains architecture-specific and requires local measurement.
| Module | Composition, phase & solubility | Valence, defects & charge | Ion/electron transport & redox | Interfaces, bands & traps | Stability & degradation | Required quantitative closure | Status |
|---|---|---|---|---|---|---|---|
| CommercialStack Oxide electrical core | HfOx/NbO2 stoichiometry, TiN/Cu phases and Al2O3/SiO2 thickness. | O-vacancy populations, Hf/Nb valence, fixed charge and Cu oxidation state. | VCM, threshold transition, leakage and unintended Cu migration must be separated. | TiN/HfOx, selector/cell and dielectric band offsets, traps and contact resistance. | Self-heating, Cu diffusion, dielectric stress, drift and cycling damage. | Composition maps, threshold/hold distributions, diffusion bounds, yield, retention and full-cell energy. | Known families; combined flow unqualified. |
| CommercialStack ITO/ZnO tile | ITO carrier composition, ZnO stoichiometry, texture and interface phases. | O-vacancy and dopant-dependent carrier density. | Photocarrier generation, recombination, dark current and bias drift. | Optical/electrical offsets, sputter damage and bonded interface loss. | Indium diffusion, humidity response, optical ageing and delamination. | Responsivity, loss, noise, lifetime, alignment tolerance and optical-to-decision system energy. | Known materials; bonded module unqualified. |
| PremiumStack Ag/Li/Te reservoir | Ag–Te, Cu–Te or (Ag,Li)–Te phases, fractions, solubility and segregation. | Ag/Cu/Li/Te valence, mobile-ion inventory and charge compensation. | Metal release, Li insertion, plating and competing fluxes must be independently attributed. | Reservoir/host offsets, ion-selective barriers, nucleation and contact potentials. | Te loss, phase separation, irreversible metal residue and self-discharge. | Activities, transference numbers, D(T,state), release law, reversibility and matched charge controls. | Buffered and co-ionic reservoir hypotheses. |
| PremiumStack Compensated fluorosulfide | Ho/Sc/Ca/S/F phase map, dopant occupancy, solubility and secondary phases. | Measured Ca/F/vacancy compensation, trap charge and local defect complexes. | S/F defect motion, electronic leakage and Li-associated transport require separation. | Reservoir/host band offsets, space charge, passivation and electrode reactions. | S/F loss, oxidation, moisture, clustering and thermal/bias ageing. | Composition-resolved Ef, Em, D(T), permeability, leakage and switching distributions. | G14–G16 material system remains exploratory. |
| PremiumStack G22/G9/G23 integration | Every plane, via, ITO/ZnO and Bi2Te3 phase and bonded-interface product. | Plane-to-plane defects, optical carriers and Bi/Te defect-controlled Fermi level. | Vertical electrical transport, photocarriers and spin-charge conversion remain separate pathways. | Via resistance, optical loss, spin transparency, interface dipoles and thermal boundaries. | Compound yield, heat, oxidation, delamination and transducer ageing. | Vertical yield, loss/noise budgets, conversion efficiency, bond yield and complete task energy. | Optional heterogeneous modules; electrical core comes first. |
| DieuModeStack NV-diamond / Si-28 | Diamond purity, NV density/site distribution and Si isotopic fraction. | NV charge state, surface termination, paramagnetic defects and residual nuclear-spin bath. | Spin, optical and microwave transitions; no ionic-memory function is presumed. | Diamond contact states, optical collection interface and control-die coupling. | Charge-state drift, surface noise, implantation damage and package strain. | Defect density, charge-state fraction, coherence, photon rate, transduction loss and natural-Si controls. | Research transducer; system benefit unproven. |
| DieuModeStack Graphene / h-BN / carbyne | Layer number, grain structure, contamination, h-BN thickness and verified carbon-chain structure. | Carrier density, edge/point defects, trapped charge and contact-induced doping. | 2D transport, tunnelling and bounded one-dimensional transport must be measured separately. | Graphene/h-BN alignment, metal contacts, tunnel barriers, residues and strain. | Oxidation, chain rupture, dielectric breakdown, delamination and mobility ageing. | Mobility, noise, contact resistance, leakage, breakdown, chain lifetime and device yield. | Heterostructure hypothesis; carbyne is the limiting idealization. |
| DieuModeStack Au / Os / TaN / TaC | Metal/carbide/nitride phases, stoichiometry, texture and interfacial products. | Work function, oxidation state, vacancies and possible OsO4 formation pathway. | Electronic contact transport, diffusion and spin-orbit response where explicitly tested. | Contact barriers, adhesion, Fermi-level pinning and refractory-layer reactions. | Au diffusion, Os oxidation/EHS, TaN/TaC stress, corrosion and thermal cycling. | Contact resistance, diffusion coefficients, oxidation bounds, EHS containment, stress and unique-function controls. | Extreme research contacts; no production flow established. |
G1–G24 chemistry-evidence heatmapqualitative evidence
Visual companion to the audit table. Color indicates how directly each property family is supported for the named stack, not expected device performance.
Quantitative property closure register
| Property family | Why it controls the technology | Minimum method set | Required reporting rule |
|---|---|---|---|
| Phase equilibria & solubility | Defines whether the nominal formula exists, remains single phase, or precipitates competing compounds. | Composition-resolved XRD/Rietveld, TEM/diffraction, calorimetry where useful, and thermodynamic/DFT convex-hull modelling. | Report temperature, pressure/atmosphere, composition uncertainty, phase fractions, detection limits, and metastability. |
| Chemical potentials, activities & electrochemical window | Controls Ag/Li release, insertion, plating, sulfur/F loss, and parasitic decomposition. | Controlled-atmosphere synthesis, open-circuit potential, cyclic/step voltammetry with reference structures, coulometry, and calibrated thermodynamic modelling. | State reference electrode, scan/pulse protocol, geometry, temperature, irreversible charge, and identified reaction products. |
| Defect thermodynamics | Sets equilibrium and bias-dependent vacancies, antisites, interstitials, dopant complexes, carriers, and compensation. | Composition-matched DFT with chemical-potential bounds and finite-size corrections, EPR/XPS, positron or optical probes where suitable, and stoichiometry. | Report phase, functional/corrections, Fermi-level range, charge states, transition levels, uncertainty, and spectroscopy limits. |
| Ion kinetics & transference | Determines switching voltage, speed, volatility, retention, cross-talk, and operation across temperature. | NEB, impedance, Hebb–Wagner or blocking-electrode tests, isotope/SIMS tracing, potentiostatic transients, and temperature-dependent operando measurements. | Report D0, Em, D(T), ion/electron transference numbers, field regime, state dependence, confidence intervals, and mechanism changes. |
| Electronic structure, dielectric response & traps | Controls injection, leakage, field distribution, read margin, optical response, and defect charge state. | UPS/XPS, Kelvin probe, ellipsometry/absorption, capacitance-frequency/temperature, Hall where valid, deep-level or noise spectroscopy, and DFT. | Report work function, electron affinity, gap, offsets, permittivity versus frequency, carrier density/mobility, trap energy/density, and model assumptions. |
| Interface reactions & interdiffusion | Can replace the intended bulk mechanism with a barrier, interphase, short, dead layer, or contamination path. | Angle/depth-resolved XPS, SIMS isotope profiles, cross-sectional STEM-EDS/EELS, in-situ bias/anneal studies, diffusion couples, and interface calculations. | Report initial interface, thermal/bias budget, depth resolution, diffusion coefficient or upper bound, products, resistance, adhesion, and uncertainty. |
| Environmental & chemical stability | Controls shelf life, drift, encapsulation, safety, process compatibility, and field reliability. | Controlled humidity/O₂/temperature storage, thermal cycling, evolved-gas analysis, corrosion/outgassing tests, capped controls, and pre/post chemistry. | Use declared dose/time/temperature/humidity, uncapped and qualified-package controls, kinetics rather than one endpoint, and failure-product identification. |
| Bias-driven reaction kinetics | Separates reversible state variables from permanent decomposition and links chemistry to pulse learning. | Operando electrical plus Raman/XAS/TEM or chemical mapping, pulse-charge accounting, polarity controls, and post-mortem isotope/depth analysis. | Correlate chemical state with conductance distributions at equal delivered charge; report reversibility, Faradaic efficiency, and cycle-to-cycle uncertainty. |
| G9 optical and G23 spin chemistry | Defects and interfaces can quench emission, move the Bi₂Te₃ Fermi level, suppress surface transport, or absorb/damp the signal. | Time-resolved photoluminescence and concentration series; Hall/ARPES/weak antilocalization; magnetometry/FMR/BLS; interface spectroscopy and diffusion profiling. | Report emitter concentration/site, radiative and non-radiative rates, quantum yield, carrier density/Fermi level, spin transparency/damping, losses, ageing, and full-stack controls. |
Decision rule: no generation advances because a nominal element is associated with a desirable property. Advancement requires a measured composition and phase, a bounded competing-reaction set, a chemically attributed state variable, and an improvement over the preceding generation at matched geometry, pulse charge, temperature, and statistical confidence.
3Oxygen vs Sulfur Vacancies: Physics, Types & Scandium
Evidence boundaryA vacancy is a missing atom on a crystallographic site, not a material particle with its own ionic radius or atomic mass. Oxygen-vacancy switching is established in many oxide RRAM systems. Sulfur-defect switching is plausible in sulfides and demonstrated in some chalcogenides, but no Ho₂S₃ or Ho₂S₃:Sc memristor data in the references below establish superior mobility, analog behavior, endurance, or temperature range.
Many oxide resistive memories, including TiO₂- and HfOx-based devices, involve oxygen-defect redistribution, interfacial redox, or localized conductive paths. Depending on stack and protocol, switching can be abrupt or gradual and may or may not require electroforming. Ho₂S₃ is a phase- and defect-dependent semiconductor, but its electronic bandgap, carrier density and conductivity must be measured in the actual film. Mixed ionic–electronic conduction is a device hypothesis, not an established property of this stack: the ionic contribution, transference number and mobile species require blocking-electrode, impedance and composition-profile evidence.
What actually moves?
In vacancy language, a neighbouring anion hops into an empty lattice site, so the vacancy appears to move in the opposite direction. Depending on the material and bias, current may involve vacancy redistribution, anion motion, trapped-electron hopping, local redox, interface-barrier modulation, or a reduced conductive phase. A narrow conductive region is common, but resistive switching does not always require a single continuous filament.
\[\mathrm{O}^{2-}\ \mathrm{hop}\leftrightarrow\mathrm{apparent}\ V_{\mathrm O}\ \mathrm{motion}\qquad\vert\qquad \mathrm{S}^{2-}\ \mathrm{hop}\leftrightarrow\mathrm{apparent}\ V_{\mathrm S}\ \mathrm{motion}\]
Physical and chemical comparison
| Property | Oxygen-defect system | Sulfur-defect system | Engineering conclusion |
|---|---|---|---|
| Reference anion | O²⁻: about 1.40 Å for the six-coordinate Shannon reference; atomic mass 16.00 u | S²⁻: about 1.84 Å for the six-coordinate Shannon reference; atomic mass 32.06 u | These are matched coordination-number reference radii, not vacancy sizes or the measured coordination in Ho₂S₃. The actual local coordination depends on the cubic, monoclinic or other processed phase and must be obtained from structure refinement or local probes. |
| Electronegativity | O: 3.44 on the Pauling scale | S: 2.58 on the Pauling scale | Oxides are often more ionic and sulfides more polarizable/covalent, but electronegativity alone does not determine bond energy or switching voltage. |
| Defect formation | Controlled by oxygen chemical potential, local bonding, dopants, interfaces, and Fermi level | Controlled by sulfur chemical potential, local bonding, dopants, interfaces, and Fermi level | Formation energy must be calculated or measured for each host, phase, and charge state. |
| Migration barrier | Ranges broadly across TiO₂, HfO₂, TaOx, and other phases | Ranges broadly across sulfides and other chalcogenides | The larger/heavier S²⁻ ion can still have a lower barrier in a softer or more open lattice; mass and radius alone cannot rank mobility. |
| Electronic effect | VO can introduce donor-like states, reduced cations, and conductive suboxide paths | VS can alter local charge, coordination, trap states, and metal–sulfur bonding | The conductive state may be electronic even when ionic motion creates it. |
| Process maturity | Extensive CMOS-compatible deposition, etch, metrology, and reliability knowledge | Less mature for rare-earth sulfides; sulfur loss and stoichiometry control are major variables | Oxides currently lead industrial readiness; sulfides are a research option, not a universal replacement. |
| Environment | Many oxides are air-stable, although electrodes and oxygen exchange still require control | Sulfide surfaces may oxidize toward oxysulfides/oxides and may react with moisture depending on composition | Ho₂S₃ films require measured air/moisture stability, encapsulation studies, and sulfur-loss analysis. |
Vacancy charge-state types
Kröger–Vink notation labels effective charge relative to the perfect lattice. The dots do not mean that a bare positive ion occupies the empty site, and the stable state depends on the Fermi level and local chemistry.
| Defect type | Common notation | Interpretation | How to distinguish it |
|---|---|---|---|
| Neutral oxygen vacancy | VO× | Missing O site with no effective charge relative to the chosen reference | DFT charge-transition levels plus EPR/XPS/optical evidence |
| Ionized oxygen vacancy | VO•, VO•• | One or two effective positive charges after electron exchange | Bias- and atmosphere-dependent spectroscopy and transport |
| Neutral sulfur vacancy | VS× | Missing S site in a neutral effective state | Composition-matched DFT, EPR, XPS, and sulfur stoichiometry |
| Ionized sulfur vacancy | VS•, VS•• | One or two effective positive charges; VS•• is the charge-compensation candidate used in this dossier | Defect populations correlated with conductivity and Ca/F concentration |
| Defect complex | Examples: ScHo×–VS, CaHo′–VS•• | Associated dopant–vacancy configuration with different formation and migration energies | DFT binding energies, temperature-dependent relaxation, and local structural probes |
Digital and analog behaviour are operating regimes
Binary / abrupt regime
A localized path reaches a percolation threshold and conductance jumps between separated HRS and LRS distributions. Oxygen- and sulfur-defect devices can both behave this way, especially under large pulses or loose current compliance.
Analog / gradual regime
Incremental pulses redistribute many defects, modulate an interface, or adjust several partial paths. Both oxide and sulfide devices can support multilevel updates when geometry, pulse dose, compliance, and feedback prevent runaway filament growth.
Therefore, “O-vacancy = digital” and “S-vacancy = analog” are not material laws. The useful comparison is statistical: number of separable states, update nonlinearity and asymmetry, cycle/device variability, retention, endurance, and energy at matched geometry and pulse conditions.
Device-mechanism types
| Cell type | Representative stack | Primary state variable | Role in this program |
|---|---|---|---|
| Oxide VCM | TiN / HfOx or TiOx / inert electrode | Oxygen-defect and cation-valence distribution | Mature control for forming, analog update, endurance, and BEOL integration |
| Sulfide VCM | Au or Pt / Ho₂S₃(:Sc) / Pt | Proposed sulfur-defect, trap, and interface distribution | Tests whether the host switches without an intentionally active metal source |
| Sulfide ECM / CBRAM | Ag or Cu / Ho₂S₃(:Sc) / Pt | Metal-cation injection and metallic bridge | Separates fast Ag/Cu filamentation from host VCM |
| Hybrid ECM–VCM | Ag–Te / Ho₂S₃:Sc / Pt | Coupled active-metal and sulfur-defect pathways | Generation-4 hypothesis for volatile and retained response modes |
What scandium changes, and what it does not
Sc³⁺ is nominally isovalent with Ho³⁺, so substitutional ScHo× does not require a sulfur vacancy for charge neutrality. Its smaller six-coordinate radius can change local strain, Sc–S/Ho–S coordination, band states, vacancy formation energy, migration barriers, and vacancy–dopant binding. Any of those changes may raise or lower vacancy concentration and mobility; the sign cannot be obtained from radius alone.
1 · PhaseConfirm Ho2−xScxS₃ solubility, sites, and secondary phases
2 · DefectsCalculate and measure VS charge states, formation, migration, and binding
3 · SwitchingCompare x-series with inert and active electrodes at matched pulse dose
4 · ReliabilityReport distributions, retention, endurance, sulfur loss, and environmental drift
Minimum control matrix: HfOx VCM reference; undoped Ho₂S₃ with Pt/Pt; Ho₂S₃:Sc with Pt/Pt; and matched Au, Ag, and Cu top-electrode variants. This design distinguishes oxide versus sulfide chemistry, Sc effects, host VCM, and active-metal ECM instead of assigning every conductance change to VS.
Blue-material candidate register: oxide, sulfide, precursor, spin, and insertion controls
Scientific boundaryColour is an identification cue, not a switching mechanism. Bulk colour can change with phase, particle size, oxidation state, hydration, defects, and film thickness. CuO and Co₃O₄ are normally black; Cu₂S is dark grey to black; CoO is commonly olive-green, grey, brown, or black rather than cobalt blue. The intense blue of hydrated CuSO₄ and Prussian Blue does not make either material a direct drop-in solid-state memory film.
| Candidate | Factual identity / appearance | Potential program role | Defensible advantages | Critical limitation | Best G1–G24 placement | Required evidence |
|---|---|---|---|---|---|---|
| CuO Copper(II) oxide | CuO; monoclinic p-type semiconductor, typically black rather than blue | Low-cost VCM comparator and Cu redox reference | Oxygen-defect, Cu-valence, interface, and filament-like switching mechanisms have a substantial thin-film literature; compatible deposition routes include sputtering, ALD/CVD variants, oxidation, and solution processing. | “CMOS compatible” is process-specific: Cu mobility requires approved barriers and contamination control. CuO may reduce toward Cu2O or Cu, so switching cannot be assigned to VO alone. | G1/G2 comparator, not a replacement for the canonical HfOx G1 control | Phase-resolved XRD/Raman/XPS; oxygen-pressure series; inert-electrode cell; operando Cu valence; identical geometry and pulse-dose comparison with HfOx and Ho₂S₃. |
| Cu₂S Copper(I) sulfide | Cu₂−xS family; dark grey/black, with phase and conductivity strongly controlled by Cu deficiency | Sulfide benchmark for mixed ionic/electronic transport and coupled Cu-ECM / sulfur-defect hypotheses | Cu mobility and electronic conduction make it a useful, less compositionally complex comparator to Ho₂S₃. Sputtering, ALD/CVD variants, sulfurization, electrodeposition, and solution routes are available. | Stoichiometry, chalcocite/djurleite/covellite-like secondary phases, high leakage, and spontaneous Cu redistribution can obscure VCM versus ECM. “More stable than Ho₂S₃” must be demonstrated, not assumed. | G10 sulfide control and G3 Cu-ECM branch | Cu:S depth map and phase map; blocking versus Cu-active electrodes; isotope or operando profiling; compliance-current series separating Cu bridge formation from host/interface modulation. |
| CuSO₄·5H₂O Copper(II) sulfate pentahydrate | Intensely blue molecular hydrate; loses water stepwise on heating and is hygroscopic | Wet-chemical Cu²⁺ source, electrodeposition electrolyte, or conversion precursor for CuO/Cu₂S | Low-cost, soluble, compositionally defined Cu feedstock enables controlled solution dosing and precursor-conversion studies. | Not a credible direct BEOL active film: bound water, sulfate residue, corrosion, outgassing, and mobile contamination are severe. Cu²⁺ is not itself a metallic filament; it must undergo electron transfer, commonly through Cu²⁺ → Cu⁺ → Cu⁰ or an equivalent reduction path. | Process precursor only for G1/G2/G4 experiments | Thermogravimetry/mass spectrometry; residual S/O/H and ionic contamination after conversion; complete mass balance; compare converted film against vacuum-deposited CuO or Cu₂S. |
| CoO Cobalt(II) oxide | CoO; antiferromagnetic below its Néel temperature, usually olive-green to grey/black in bulk or films | Transition-metal dopant series or separate trap/redox-active reference layer | Co 3d states can alter band alignment, carrier density, redox chemistry, and trapping; multiple thin-film deposition routes are established. | Co incorporation may create leakage, secondary phases, or toxic-material handling burdens. Trap stabilization and improved resistive states cannot be inferred from the presence of 3d orbitals. | G5/G6 dopant comparator; interface-passivation study adjacent to G11 | Low-concentration Co series; oxidation-state/site analysis; band offsets; trap spectroscopy; leakage, retention, and variability compared with undoped host. |
| Co₃O₄ Mixed-valence cobalt oxide | Normal spinel with Co²⁺/Co³⁺, generally black; antiferromagnetic at low temperature, not a room-temperature ferromagnet by default | Mixed-valence oxide reference for redox, magnetic-order, and spin-interface experiments | Thermally robust oxide with accessible Co valence chemistry and established sputter, ALD/CVD, sol-gel, and oxidation routes. | Bulk antiferromagnetism does not establish useful spin injection, spin-wave transport, or G23 benefit. Oxygen stoichiometry and nanoscale defects can dominate both magnetism and resistance. | G1 redox control and separately qualified G23 spin-interface option | Temperature-dependent magnetometry and transport; XPS/XAS valence; exchange-bias or spin-transmission measurement with a defined magnetic partner; full nonmagnetic control stack. |
| CoAl₂O₄ Cobalt aluminate spinel | Robust cobalt-blue spinel pigment; insulating behaviour depends on stoichiometry, inversion, defects, and film quality | Structural dopant, dielectric, diffusion barrier, or trap-engineering reference | High chemical and thermal stability; spinel structure provides a controlled route to tune dielectric response and interface traps. | Its stability can also make it too insulating to switch at useful voltage. Co/Al interdiffusion, spinel inversion, and crystallization temperature may conflict with the BEOL budget. | G5/G6 structural control or G11 stability/barrier branch | Dielectric constant/loss and breakdown; band offsets; trap density; crystallization temperature; ultrathin thickness series; diffusion and switching comparison against Al₂O₃. |
| Prussian Blue Iron hexacyanoferrate framework | Idealized as Fe₄[Fe(CN)₆]₃; real films contain variable vacancies, alkali ions, and water | Open-framework Na⁺/K⁺/Li⁺ insertion benchmark and electrochromic G17 control | Open channels, mixed Fe valence, visible optical readout, and extensive battery/electrochromic literature make ion insertion easier to diagnose than in the proposed fluorosulfide. | Hydration, cyanoferrate-vacancy content, electrolyte dependence, low-temperature stability, and voltage-window limits impede direct CMOS integration. Safe synthesis and waste handling are mandatory; thermal or acidic decomposition must be avoided. | G17 insertion test vehicle, preferably gated or three-terminal and physically separate from the OMNI stack | Quartz-crystal microbalance or coulometry with operando spectroscopy; Na/K/Li selectivity; water/vacancy assay; cycling and retention; sealed electrolyte and matched non-insertion control. |
Minimum split-lot experiment for the seven candidates
| Test branch | Minimum architecture | Primary discriminator | Advance condition | Stop / fallback condition |
|---|---|---|---|---|
| CuO VCM | Pt / CuO / Pt plus oxygen-scavenging-electrode split | Oxygen-pressure and electrode dependence correlated with Cu valence | Reproducible gradual states or a useful binary control at matched pulse energy | Unbounded reduction, Cu bridge dominance, or no advantage over HfOx |
| Cu₂S mechanism | Pt / Cu₂−xS / Pt versus Cu / Cu₂−xS / Pt | Blocking-electrode response versus active-Cu injection | Separately attributable host and Cu-ECM windows with controlled leakage | Composition drift or mixed phases prevent mechanism assignment |
| CuSO₄ precursor | Converted CuO and Cu₂S coupons; no hydrate active-cell claim | Residual H, sulfate, Na/K and morphology versus vacuum controls | Converted film meets the same phase, impurity, and device distributions | Water/outgassing, corrosion, or sulfate residue exceeds process limits |
| CoO dopant | Pt / host:Co concentration series / Pt | Co site/valence and trap-density correlation | Statistical retention or variability improvement without leakage penalty | Secondary phase, increased drift, or no causal improvement |
| Co₃O₄ spin/redox | Electrical cell plus separate magnetic-interface test coupon | Resistance switching separated from measured spin transmission or exchange effect | Reproducible magnetic contribution beyond thermal and redox controls | No room-temperature spin benefit; retain only as oxide redox control |
| CoAl₂O₄ dielectric | Electrode / 1–10 nm CoAl₂O₄ / host / electrode | Barrier, trap, leakage, and breakdown versus Al₂O₃ | Improved stability or update control within voltage/thermal limits | Excess voltage, crystallization temperature, or added variability |
| Prussian Blue insertion | Gated or three-terminal ion-insertion transistor with sealed electrolyte | Charge-balanced mass/optical/conductance response for Li⁺, Na⁺, and K⁺ | Reversible insertion produces separable short/long timescale states | Water loss, framework degradation, parasitic redox, or poor retention; use established oxide ECRAM control |
Portfolio rule: these candidates extend the control library without creating additional generations. CuO and Co₃O₄ strengthen oxide/redox references; Cu₂S tests a simpler sulfide and Cu-ECM pathway; CuSO₄·5H₂O is restricted to precursor work; CoO and CoAl₂O₄ test dopant/barrier hypotheses; and Prussian Blue isolates ion-insertion physics before G17/G21.
O²⁻/S²⁻ radii and O/S atomic properties
Ionic radii are matched six-coordinate Shannon references, not an assertion about the local coordination in a particular Ho₂S₃ phase. Atomic mass and Pauling electronegativity apply to neutral-element reference data for O and S. Bars are normalized within each property only.
Evidence ladder by mechanism
Qualitative dossier status, not a performance score. Higher means more directly established for the named material system.
4Ho₂S₃:Sc Scientific Basis & Validation
This section isolates the scandium-doped host from the complete co-ionic stack. Ho₂S₃:Sc denotes substitutional Ho2−xScxS₃; the actual phase, site occupancy, and solubility limit must be measured for every value of x.
Lattice strain and composition series
For six-coordinate ions, Shannon radii of 0.901 Å for Ho³⁺ and 0.745 Å for Sc³⁺ give a Ho-referenced relative mismatch of (0.901 − 0.745) / 0.901 = 17.3%. This supports a local-distortion hypothesis, but it does not determine a macroscopic strain value or prove that sulfur-vacancy formation energy decreases. A minimum composition series is x = 0, 0.05, 0.10, 0.20, and 0.30, with phase purity checked before electrical comparison.
- XRD/Rietveld: lattice parameters, secondary phases, crystallite size, and microstrain versus x.
- STEM-EDS/EELS: Sc site occupancy, clustering, and any ordered dopant rows.
- DFT/NEB: sulfur-vacancy formation energies and migration barriers for multiple Sc–vacancy configurations.
\[\mathrm{Mismatch}=\frac{r_{\mathrm{Ho}^{3+}}-r_{\mathrm{Sc}^{3+}}}{r_{\mathrm{Ho}^{3+}}}=\frac{0.901-0.745}{0.901}=0.173\]
Six-coordinate ionic-radius comparison
Shannon effective radii. The 17.3% mismatch motivates a local-distortion study; it does not establish the sign of strain or defect energetics.
Sc composition series: measurement map
No monotonic trend is assumed. Every concentration is measured before selecting an optimum.
Filamentation and variability
Sc substitution may alter local defect energies and therefore bias vacancy nucleation. A repeated path is only demonstrated if operando imaging or post-cycle nanoscale mapping correlates the conductive channel with Sc-rich sites. Variability must be reported separately as CVC2C(VSET) within each device over cycles and CVD2D(VSET) across device-level means; pooling both populations into one σ/μ obscures different physical mechanisms. The <2% objective applies independently to both metrics unless a narrower scope is explicitly declared.
Undoped host: unconstrained-path hypothesis
Concept only. Multiple possible paths represent an unresolved defect-energy landscape, not measured Ho₂S₃ filaments.
Sc-doped host: biased-path hypothesis
Concept only. Sc sites may alter local energies; an ordered rail or repeatable filament has not been observed.
| Metric | Required report | Proposed acceptance target |
|---|---|---|
| SET/RESET voltage | Per-device cycle distributions, distributions of device means, CVC2C, CVD2D, and the hierarchical sample structure over ≥100 devices and ≥100 cycles/device | G14 intermediate gate: VSET < 0.5 V with both CVC2C and CVD2D < 2%; 0.2 V is the later G16/G21 system target |
| ON/OFF ratio | Read-voltage-defined HRS/LRS distributions with confidence intervals | ≥10³ without overlap of read distributions |
| Endurance | Continuous pulse cycling with failures and compliance current disclosed | G3 gate: ≥10⁹ cycles while retaining the specified window |
| Analog update | Potentiation/depression curves, nonlinearity, asymmetry, noise, and effective bits | Gradual bidirectional updates; 10-bit is a stretch target |
Band structure and leakage
Hybridization among Ho 4f, Sc 3d, and S 3p states is chemically plausible, but the direction and size of the bandgap change cannot be inferred from orbital labels. No composition- and phase-matched DFT or experimental source in this dossier supports a numerical bandgap bracket for the proposed thin films, so none is asserted. Optical absorption, ellipsometry, ultraviolet photoelectron spectroscopy, and composition-matched DFT are needed. ON/OFF ratio must be measured independently because it also depends on interfaces, defects, thickness, filament geometry, and read bias.
Thermal stability, retention, and electromigration
The 1.0 eV degradation barrier used below is hypothetical and illustrative, not a measured activation energy for Ho₂S₃:Sc. High bond strength does not by itself establish device retention. A ten-year claim at 150 °C or 200 °C requires an Arrhenius model supported by several accelerated temperatures and a measured activation energy. Under the illustrative 1.0 eV assumption, acceleration relative to 25 °C is approximately 9.9 × 10⁴ at 150 °C and 1.8 × 10⁶ at 200 °C; changing the fitted barrier changes the projection by orders of magnitude.
- Retention: test HRS and LRS at no fewer than three elevated temperatures; report raw drift and confidence bounds before extrapolation.
- Electromigration: use SIMS/TEM depth profiles before and after cycling to distinguish Ag/Li ingress from sulfur-vacancy motion.
- Thermal phase stability: use XRD/XPS after 150 °C, 200 °C, and BEOL-relevant anneals; electrical survival alone is insufficient.
What can and cannot currently be claimed
Supported or recalculable
Ho₂S₃ is an established compound; Sc³⁺ can be considered as an isovalent Ho³⁺ substituent; the six-coordinate radius mismatch is 17.3%; 10¹⁰ cells/cm² corresponds to a 100 nm square pitch; 0.5 pJ at 0.2 V permits a 2.5 pC integrated-charge budget.
Unvalidated design targets
Ordered Sc rails, deterministic filamentation, Ea < 0.6 eV, separate CVC2C and CVD2D < 2%, G14 sub-0.5 V switching, 10³–10⁶ ON/OFF ratio, G14 endurance ≥10⁹ cycles, symmetric LTP/LTD, and ten-year retention above 150 °C.
How the supplied prototype claims translate into research tasks
| Prototype statement | Status in this dossier | Evidence required before publication |
|---|---|---|
| Sc lowers vacancy formation energy monotonically | Directional hypothesis; the trend may be non-monotonic or phase-dependent | Composition-resolved DFT/NEB checked against spectroscopy and transport activation energies |
| The same filament forms every cycle | Filament-bias objective, not a demonstrated deterministic rail | Operando or statistically correlated nanoscale maps over cycles and devices |
| Sc widens the bandgap to about 4 eV | Unvalidated sign and magnitude | Ellipsometry/absorption, UPS/XPS, phase-matched DFT, and uncertainty reporting |
| G14: sub-0.5 V, CVC2C and CVD2D < 2%, ≥10⁹ cycles | Intermediate acceptance targets; cycle-to-cycle and device-to-device variability are evaluated separately, while 0.2 V and ≥10¹⁰ cycles are later G16/G21 program targets | Blind device populations, disclosed compliance/pulses, hierarchical distributions, failures, and raw endurance traces |
| Retention above 150 °C for ten years | Accelerated-life target | Multiple temperatures, justified Arrhenius model, confidence bounds, and post-test phase/interface analysis |
| Patentable material platform | Potential IP subject, not a legal conclusion | Prior-art search, novelty/inventive-step analysis, enabling examples, ownership review, and counsel |
5Electrochemical Mechanism
5.1 · A Buffered Cation Reservoir, Not a Bare Metal
In conventional CBRAM with a pure silver electrode, anodic oxidation accelerates once the threshold is reached, injecting a burst of Ag⁺ that grows an abrupt, oversized filament:
\[\mathrm{Ag}\rightarrow\mathrm{Ag}^{+}+e^{-}\]
NEURO-SYNAPSE-OMNI proposes replacing the pure metal with a silver–tellurium chalcogenide containing Ag₂Te-like phases. The experiment tests whether field-assisted dealloying can release Ag⁺ more progressively than a pure-Ag electrode and thereby widen the analog programming window. A general reservoir half-reaction avoids assuming that elemental Te is the unique product:
\[\mathrm{Ag}_{x}\mathrm{Te}_{y}(s)\rightleftharpoons\mathrm{Ag}_{x-\Delta}\mathrm{Te}_{y}(s)+\Delta\mathrm{Ag}^{+}+\Delta e^{-}\qquad\text{(candidate field-assisted dealloying)}\]
The residual phase may instead reconstruct, segregate, oxidize, or form another Ag–Te stoichiometry. Phase identity, Ag chemical activity, Te oxidation state, release rate, pulse-to-pulse dose, and any buffering advantage require composition-resolved XRD/XPS, microscopy, coulometry, and depth profiling.
5.2 · Co-Ionic Division of Labor
Ag⁺ is hypothesized to provide the faster pathway by assembling a thin filament that may dissolve when the bias is removed. A decay constant on the order of tens of milliseconds is an illustrative target, not a measured fact for this stack. Li⁺ is intended to produce a slower retained host-composition change:
\[x\mathrm{Li}^{+}+xe^{-}+(\mathrm{Ho,Sc,Ca})_2(\mathrm{S,F})_3\rightleftharpoons\mathrm{Li}_x(\mathrm{Ho,Sc,Ca})_2(\mathrm{S,F})_3\quad\text{(candidate retained insertion reaction)}\]
The program targets 1,024 statistically separable conductance states for 10-bit functional weight resolution. Whether Li⁺ insertion and volatile Ag⁺ dynamics can produce retained LTP, paired-pulse facilitation, and STDP-compatible responses must be established experimentally.
5.3 · Lattice-Strain Hypothesis (Scandium)
Six-coordinate reference radii have a 17.3% Ho-referenced mismatch for Ho³⁺ and Sc³⁺. This motivates, but does not determine, a local-distortion hypothesis. Because Sc³⁺ is isovalent with Ho³⁺, it does not create sulfur vacancies for charge neutrality; DFT/NEB and structural measurements must establish whether it raises or lowers vacancy formation and migration energies. Ordered Sc³⁺ rows, an atomic rail, improved linearity, and independent CVC2C(VSET) and CVD2D(VSET) < 2% remain unmeasured hypotheses.
5.4 · Forming-Free Operation (Calcium)
Aliovalent Ca²⁺ on a Ho³⁺ site has one negative effective charge, CaHo′. Although an F⁻ ion is negatively charged in absolute terms, F⁻ on an S²⁻ site has one positive effective charge relative to the lattice, FS•; a sulfur vacancy has two, VS••. For the formal defect model Ho2−x−yScxCayS3−z−δFz, assuming Ho³⁺, Sc³⁺, Ca²⁺, S²⁻ and F⁻ with no mixed valence, interstitials or electronic compensation, neutrality is −y + z + 2δ = 0, hence y = z + 2δ. Whether this model describes the processed film, and whether the resulting defect population creates a percolation path and enables 0.2 V forming-free switching, are experimental questions.
5.5 · Rad-Hard Passivation (Fluorine)
Ho–F bonding may passivate part of the defect landscape. Total-ionizing-dose resistance, cryogenic ionic mobility, and chemical stability through 450 K are independent test requirements and cannot be inferred from bond strength alone.
6Co-Ionic Dynamics: Two Timescales, One Synapse
A biological synapse multiplexes fast signalling with slower plasticity. NEURO-SYNAPSE-OMNI is designed to test an analogous two-timescale response, with the balance between proposed Ag⁺ and Li⁺ pathways controlled by pulse amplitude, duration, count, and spacing.
NEURO-SYNAPSE-OMNI proposes to investigate these limitations with a co-ionic architecture. An (Ag,Li)-Te ionic supply layer is intended to test two candidate cation pathways: Ag⁺ for volatile short-term plasticity and Li⁺ for a slower retained insertion response. In the proposed (Ho,Sc,Ca)₂(S,F)₃ active matrix, Sc³⁺ is an isovalent experimental variable that may alter defect energetics but does not create sulfur vacancies for charge neutrality. Under the formal fixed-valence substitution/vacancy model, Ca²⁺, F⁻, and sulfur vacancies satisfy y = z + 2δ; other compensation channels must be tested. The 10-bit, separate CVC2C and CVD2D < 2%, 0.2 V, radiation-tolerance, and 4 K – 450 K figures remain experimental targets.
Short-Term Plasticity Target — Ag⁺
A weak pulse is intended to extract a limited Ag⁺ dose and form a narrow, incomplete filament. The illustrative target τ ≈ 25 ms represents a candidate spontaneous conductance decay to be measured, not an established property.
Long-Term Plasticity Target — Li⁺
Repeated or stronger pulses are intended to drive Li⁺ insertion into the host. Multi-year retention and 1,024 separable levels are targets requiring direct structural and electrical validation.
Dual ionic response after an identical pulse train
Normalized conductance vs. time. Ag⁺ (cyan): illustrative volatile STP target with τ ≈ 25 ms. Li⁺ (gold): illustrative retained LTP target. All curves and decay constants must be measured on fabricated cells.
8Calcium G16 & Lithium Co-Ionic G21
Evidence boundaryAliovalent charge compensation, lithium intercalation, ECM filamentation, and calcium-dependent biological plasticity are established concepts. Their coexistence and numerical performance in this exact material stack have not been demonstrated.
G16 · Ca/F-Compensated Forming-Free Synapse
Replacing Ho³⁺ or Sc³⁺ with Ca²⁺ creates one negative effective charge per substitution. Charge neutrality can be restored by positively charged sulfur vacancies, by F⁻ occupying S²⁻ sites, or by a mixture of both:
\[2\mathrm{Ca}_{\mathrm{Ho}}^{\prime}+V_{\mathrm S}^{\bullet\bullet}\rightleftharpoons0\qquad\text{and}\qquad\mathrm{Ca}_{\mathrm{Ho}}^{\prime}+\mathrm F_{\mathrm S}^{\bullet}\rightleftharpoons0\]
\[\mathrm{Ho}_{2-x-y}\mathrm{Sc}_x\mathrm{Ca}_y\mathrm S_{3-z-\delta}\mathrm F_z:\qquad y=z+2\delta\]
Thus Ca doping gives a rational route to tune the initial defect population and possibly reduce or eliminate electroforming. It does not prove a pre-existing conductive path: too few vacancies may leave forming necessary, while too many may increase leakage, collapse retention, or short the device.
| G16 hypothesis | Required control | Acceptance evidence |
|---|---|---|
| Forming-free operation | Undoped, Ca-only, F-only, and Ca+F cells with identical thickness and electrodes | First-cycle switching at the operating voltage across a statistically meaningful device population |
| Vacancy creation | Composition series in y, z, and δ | XPS/EPR or complementary defect analysis correlated with conductivity |
| Strain relaxation | Sc-only versus Sc+Ca compositions | Rietveld/TEM strain mapping plus lower cycling-induced structural drift |
| Endurance improvement | Same pulse energy and compliance current | G16 gate: ≥10¹⁰ cycles; >10¹² cycles is a separate exploratory stretch target |
Using six-coordinate Shannon radii, Ca²⁺ is about 1.00 Å, compared with Ho³⁺ at 0.901 Å and Sc³⁺ at 0.745 Å. Opposing size mismatches may alter average strain, but they do not guarantee perfect cancellation because local coordination, dopant distribution, phase stability, and defect association control the real strain field.
Biological analogy: useful but not chemical identity
In biological synapses, Ca²⁺ influx through NMDA receptors and other channels participates in signalling cascades that regulate LTP and LTD. In the proposed solid, Ca²⁺ is primarily a structural dopant used to tune charge compensation and defects; it is not yet shown to be the mobile programming signal. The defensible description is calcium-inspired defect engineering, not absolute biological isomorphism.
G21 · Ag/Li Single-Cell Dual-Timescale Synapse
Li⁺ may occupy available interstitial or insertion sites and modify electronic conductivity over a larger active volume than a narrow Ag filament. This can, in principle, support more gradual updates. Before calling the process intercalation, diffraction, spectroscopy, depth profiling, and coulometric measurements must distinguish reversible host insertion from plating, conversion reactions, irreversible trapping, and interface accumulation.
\[x\mathrm{Li}^{+}+xe^{-}+\mathrm{Host}\rightleftharpoons\mathrm{Li}_x\mathrm{Host}\]
Ten-bit operation means at least 1,024 reliably separable conductance levels, not merely 1,024 programming pulses. The minimum evidence is repeated program/read distributions over devices, with drift, noise, retention, nonlinearity, asymmetry, and ADC resolution included. “Infinitely smooth,” perfectly linear, and biologically equivalent updates are not physically defensible specifications.
Cryogenic and quantum compatibility
Low lithium mass can increase nuclear quantum effects, but mass alone does not establish useful Li⁺ transport at 4 K. In the absence of a measured low-barrier mechanism, useful Li insertion should be presumed frozen at 4 K because classical hopping is exponentially suppressed. In a simple WKB picture, tunnelling probability decreases approximately exponentially with barrier width and with the square root of barrier height; attempt frequency, lattice coupling, available sites, electric field and dissipation also affect the net rate. Published cryogenic memristors show that some resistive devices can operate near liquid-helium temperature, but this is not evidence for lithium tunnelling in the proposed fluorosulfide.
\[P \propto \exp\!\left(-\frac{2a\sqrt{2m\Delta E}}{\hbar}\right)\]
Quantum-ready qualification requires temperature-dependent I–V and pulse measurements from 300 K to 4 K, extraction of the transport law, retention after thermal cycling, local heat-load measurement, and verification that programming noise does not disturb nearby qubits. The realistic fallback is to program Li-dependent retained state at 77–300 K and place only a qualified read path, Ag/VCM temporal element, or conventional cryo-CMOS cache at 4 K. Active Li programming at 4 K remains a stop-gated research target; placement beside a quantum processor is a later system-integration milestone.
Comparison of internal transport pathways
| Pathway / species | Proposed physical role | Expected strength | Main risk | Status here |
|---|---|---|---|---|
| Ag⁺ / ECM | Fast metallic filament growth and dissolution | Low-voltage, fast, potentially volatile STP | Abrupt SET, overgrowth, metal contamination, variability | Hypothesis for this stack |
| Li⁺ insertion | Candidate distributed host-composition and conductance change | Potentially gradual retained response to test | Slow kinetics, trapping, phase change, thermal drift | Unverified in this host |
| S/F vacancies / VCM | Anion-defect migration and local redox | Host-controlled switching without a metal bridge | Defect clustering and stochastic paths | Requires inert-electrode controls |
| Ca²⁺ dopant | Aliovalent defect and forming-voltage control | Native vacancy tuning | Leakage if over-doped; compensation may occur through F instead | G16 design variable |
| Sc³⁺ dopant | Local strain and defect-energy modification | Possible nucleation bias | Clustering or secondary phases; no proven atomic rail | Structural hypothesis |
| F⁻ substitution | Charge compensation and defect passivation | Possible leakage and stability control | Reduced vacancy population or altered phases | Requires composition mapping |
7G4 · Ag Hybrid-Plasticity Synapse
Active reservoir selection: gold, silver, copper, AgCu, and lithium
Ag and Cu are valid active-metal candidates for electrochemical metallization cells. Au is comparatively noble and is normally treated as an inert electrode rather than a ready source of mobile cations. None is universally superior: oxidation potential, ion mobility, nucleation, filament morphology, electrolyte chemistry, interfaces, current compliance, and pulse protocol jointly determine performance. Li⁺ belongs in a separate category because the intended mechanism is host insertion rather than a direct replacement for an Ag/Cu metallic filament.
| Candidate | CMOS / foundry fit | Speed & energy | Filament control | Quebec strategy | Development verdict |
|---|---|---|---|---|---|
| Au inert electrode | Useful in laboratory test structures because it is conductive and chemically resistant; costly and not a standard active CBRAM source. | No expected Au-cation ECM path under ordinary operating conditions; switching would rely mainly on host defects, interfaces, or another active species. | Suppresses the intended Ag/Cu metallic bridge, making it a valuable VCM control rather than a fast-filament candidate. | Gold is mined in Quebec, but cost and process purpose matter more than prestige. | Best inert control for separating host VCM from active-metal ECM, subject to interface reactions. |
| Ag–Te | Ag is less conventional in CMOS lines and requires dedicated contamination barriers and qualification. | Ag⁺ often offers high mobility and low-voltage, fast ECM switching; the advantage is electrolyte-dependent. | Fast growth can become abrupt or dendritic; Te buffering may moderate release but must be measured. | Silver and tellurium are available as products or by-products of Quebec polymetallic and refining activity. | Best candidate for the fast-path baseline, subject to diffusion control. |
| Cu–Te | Cu is established as an interconnect metal, but mobile Cu is still a tightly controlled contaminant outside approved Cu modules. Integration is plausible, not automatic. | Cu ECM can be fast and low-energy, although it may require different fields or pulses than Ag. | Slower nucleation in some electrolytes can improve filament controllability and retention; no universal advantage exists. | Quebec has a stronger large-volume copper mining, smelting, and refining narrative than for specialty silver. | Priority industrial alternative for foundry and sovereign-supply evaluation. |
| AgCu–Te | Introduces two mobile metals and therefore a more complex contamination, composition, and process-control problem. | May combine rapid Ag response with Cu-assisted stabilization if their release potentials can be separated. | Could tune nucleation, but mixed filaments may segregate, drift in composition, or add variability. | Uses Canadian Ag and Cu; alloy composition and Te supply remain qualification variables. | Useful transition experiment, not automatically a “super-alloy.” |
| (Ag,Li)–Te | Li adds a highly mobile contamination species and demands barriers, dedicated tooling, and thermal-budget validation. | Targets fast Ag-mediated STP plus slower Li-mediated LTP rather than one optimized filament. | Potentially broadens analog control, but pathway interference and Li trapping are major risks. | Connects Quebec silver/tellurium with the province’s lithium resource base. | Highest-functionality research option; also the highest integration complexity. |
| Li-only insertion source | Not equivalent to an ECM metal electrode; normally requires a compatible insertion host, ion conductor, and often a three-terminal architecture. | Usually slower than metallic-filament switching but potentially more gradual. | Distributed state may improve analog updates; retention, plating, and phase stability must be controlled. | Strong Quebec lithium narrative, but device-grade chemicals and processing must also be localized. | Benchmark as an ECRAM-like control, not as a drop-in Ag replacement. |
Unified comparison of metals, conductive electrodes and ionic reservoirs
Comparison boundaryThis matrix places every metallic or conductive candidate used in the electrical stack on one page. TiN is a conductive ceramic, while Ag–Te, Cu–Te, AgCu–Te and (Ag,Li)–Te are reservoirs rather than pure metals. HfOx, NbO2, ITO and ZnO remain in the premium-material audit as functional compounds; their behavior cannot be inferred from elemental Hf, Nb, In, Sn or Zn.
| Candidate | Primary role | Electrical / ionic behavior | CMOS / foundry fit | Pros | Cons | Relative cost / scarcity | Recommended use |
|---|---|---|---|---|---|---|---|
| Au | Inert counterelectrode; exploratory active species | Excellent electronic conductor; comparatively noble, so repeatable Au+ injection is electrolyte- and interface-dependent. | Poor for mainstream silicon lines; dedicated tools and diffusion control normally required. | Chemically resistant contact; useful VCM control; optical compatibility. | Very expensive; adhesion/diffusion issues; weak default case as an ECM source. | $$$$$ | Isolated prototypes and inert controls; active ECM only after direct evidence. |
| Ag | Active ECM electrode | Readily oxidized to mobile Ag+ in suitable electrolytes; rapid metallic bridge formation. | Nonstandard mobile contaminant requiring segregation, barriers and accounting. | Fast, low-voltage ECM precedent; strong volatile-STP candidate. | Abrupt SET, dendrites, residual metal, shorts and variability. | $$$$ | Fast-path reference with charge compliance and matched inert controls. |
| Cu | Active ECM electrode; interconnect metal | Mobile Cu+/Cu2+ can plate into a metallic bridge; kinetics depend on electrolyte. | Mature inside qualified Cu modules, but mobile Cu remains tightly controlled elsewhere. | Industrial supply and barrier expertise; potentially controllable ECM; lower cost than Ag/Au. | Diffusion contamination, corrosion and filament retention/variability. | $$ | Priority scalable ECM comparator and industrial fallback. |
| Li | Insertion ion / retained-state source | Li+ targets distributed insertion or interfacial accumulation, not a conventional metallic bridge. | Highly mobile contamination species; compatible host, ion conductor and dedicated module required. | Potential gradual volumetric state and slower retention timescale; strategic Canadian supply. | Trapping, plating, phase change, moisture sensitivity and slow kinetics. | $$$ | ECRAM-like control or paired retained-state device, not an Ag/Cu substitute. |
| Pt | Inert counterelectrode and laboratory reference | Stable high-work-function electronic contact with low intended ionic participation. | Used in research and specialty processes; expensive and not preferred for dense commodity interconnect. | Strong inert baseline; thermal and chemical stability; clean mechanism discrimination. | High cost, difficult etch and integration burden; no active-ion functionality. | $$$$$ | Reference electrode for mechanism studies and high-value prototypes. |
| TiN | Scalable electrode, barrier and line | Conductive ceramic; work function and oxygen-scavenging behavior depend on stoichiometry and interface. | Strong CMOS/BEOL precedent with established deposition and patterning. | Low series resistance, robust barrier role, scalable and comparatively economical. | Can react with or scavenge oxygen from HfOx; properties vary with N/O content. | $$ | Default scalable premium electrode after interface qualification. |
| W | Interconnect, via, heater or inert-electrode comparator | Refractory conductor; interface oxides and work function can still affect switching. | Established semiconductor metallization and contact ecosystem. | High-temperature stability, mechanical robustness and mature integration routes. | Difficult etch/stress, possible WOx interphase and no active ECM-ion role. | $$ | Industrial electrode/interconnect comparator, not the mobile species. |
| Ag–Te | Buffered Ag reservoir | Composition-dependent Ag activity intended to meter Ag+ release. | Ag/Te contamination and phase qualification require dedicated process controls. | May retain Ag speed while widening the incremental programming window. | Te scarcity, phase drift, interdiffusion and possible over-buffering. | $$$$ | Preferred fast-path reservoir research baseline. |
| Cu–Te | Buffered Cu reservoir | Composition-dependent Cu activity and Cu-ion injection. | Leverages Cu knowledge, but Te and mobile-Cu placement remain controlled. | Potentially better foundry narrative and sovereign supply than Ag–Te. | Unproven release law, Te phase variability and possibly higher programming field. | $$$ | Priority industrial reservoir alternative. |
| AgCu–Te | Mixed active-metal reservoir | Targets rapid Ag response plus Cu-assisted nucleation or stabilization. | Two mobile metals increase contamination, metrology and composition burden. | Large tuning space and possible speed/control compromise. | Segregation, mixed-filament drift and difficult causal attribution. | $$$$ | Bounded composition series only after Ag–Te and Cu–Te baselines. |
| (Ag,Li)–Te | Co-ionic fast/slow reservoir | Proposed Ag ECM plus slower Li insertion or interfacial state. | Highest contamination and thermal-budget burden among electrical reservoirs. | Potential native STP/LTP and compact temporal processing. | Pathway interference, Li trapping, irreversible products and complex control. | $$$$$ | Frontier G21 experiment; paired G19 devices remain the fallback. |
What changes when Ag is replaced by Au?
With Ag, anodic oxidation can inject mobile metal ions and cathodic reduction can build a conductive bridge:
\[\mathrm{Ag}\rightleftharpoons\mathrm{Ag}^{+}+e^{-}\qquad\vert\qquad\mathrm{Ag}^{+}+e^{-}\rightleftharpoons\mathrm{Ag}^{0}\]
Gold has a much lower tendency to oxidize under comparable device conditions. Replacing Ag with Au therefore removes the intended Ag-ECM contribution. It does not guarantee that resistive switching disappears: an Au / Ho₂S₃:Sc / Pt device could still switch through sulfur-vacancy redistribution, interface barriers, traps, local redox, or unintended electrode reactions. The correct host-controlled reference is G14 with an inert electrode; G20 remains a separate active-Au experiment.
| Test architecture | Dominant mechanism to test | Expected plasticity hypothesis | Scientific purpose |
|---|---|---|---|
| Au / Ho₂S₃:Sc / Pt | Host VCM, traps, and interfaces; Au treated as nominally inert | Likely non-volatile or slowly relaxing response if host defects dominate | Baseline separating matrix behaviour from active-metal injection |
| Ag / Ho₂S₃:Sc / Pt | Ag ECM plus possible sulfur-vacancy VCM | Volatile STP may occur for incomplete filaments; stronger pulses may produce retained states | Minimal hybrid bimodal candidate |
| Cu / Ho₂S₃:Sc / Pt | Cu ECM plus possible sulfur-vacancy VCM | Potentially slower or more stable filament response, strongly electrolyte-dependent | Industrial active-metal alternative |
| (Ag,Li)–Te / doped fluorosulfide / Pt | Ag ECM + Li insertion + anion-defect VCM | Designed for multiple timescales, with the greatest risk of pathway coupling | Full G21 research stack |
Ag / Ho₂S₃:Sc bimodal hypothesis
In the minimal hybrid cell, weak or brief pulses may create an incomplete Ag filament that dissolves after the field is removed, producing a volatile conductance transient analogous to STP. Repeated or stronger pulses may thicken the metallic path, alter sulfur-vacancy distributions, or change interfaces, producing longer retention analogous to LTP. This history dependence is physically plausible in ECM/VCM systems, but it is not guaranteed by Ag–S affinity and cannot be assigned a nanosecond speed or sub-picojoule energy without measured current transients.
G4 reference architecture and proof program
G14 is the inert-electrode Ho₂S₃:Sc host experiment. G4 is the simpler Ag-ECM reference; combining its active Ag source with the G14 host is a cross-module experiment that must separate Ag oxidation, transport and reduction from host-controlled VCM.
\[\text{Active electrode: }\mathrm{Ag}\rightarrow\mathrm{Ag}^{+}+e^{-}\qquad\vert\qquad\text{counter-electrode: }\mathrm{Ag}^{+}+e^{-}\rightarrow\mathrm{Ag}^{0}\]
The electric field provides a directional Ag⁺ transport path through the sulfide electrolyte. A conductive bridge forms only if injection, transport, nucleation, and reduction all occur within the selected voltage, pulse-width, and compliance-current window. Sulfur vacancies VS•• may simultaneously redistribute, but two mobile defect species do not by themselves prove two independently addressable memory channels.
| Canonical module | Ag implementation | Intended response | Key trade-off | Required discriminator |
|---|---|---|---|---|
| G4-A · Active electrode | Continuous Ag top electrode / Ho₂S₃:Sc / Pt | Direct ECM baseline; volatile or retained filament according to pulse dose | Simple fabrication, but abrupt SET and filament overgrowth are possible | Compare with Au / Ho₂S₃:Sc / Pt at matched geometry |
| G4-B · Embedded nanoclusters | Controlled Ag nanoparticles or nanoclusters inside or at the surface of Ho₂S₃:Sc | Distributed nucleation sites and potentially lower path length | Cluster size, spacing, percolation, and coarsening may increase leakage or variability | TEM/EDS before and after cycling plus cluster-free controls |
| G12 · Buffered reservoir | Ag–Te source / qualified host / Pt | Metered Ag⁺ release intended to widen the analog pulse window | Additional phase chemistry and Te/Ag diffusion qualification | SIMS profiles and pure-Ag G4 reference at equal delivered charge |
| G4-D · Hybrid selector cell | G4-A, B, or C integrated as 1T1R or 1S1R | Array-compatible compliance and suppression of sneak currents | Selector voltage, area, variability, and BEOL thermal budget | Array statistics rather than isolated-cell best cases |
Fast / volatile branch
A subcritical or narrow Ag bridge may relax after the pulse and produce STP-like conductance decay. This must be demonstrated through time-resolved decay distributions, not inferred solely from the presence of silver.
Consolidated / retained branch
Pulse repetition may stabilize a thicker Ag path, alter interfaces, or reorganize VS••, producing LTP-like retention. Chemical mapping is needed to identify which mechanism stores the retained state.
Performance boundary: Ag-based sulfide ECM can operate at low voltage and short pulse width in suitable devices, but <0.2 V, nanosecond switching, near-zero energy, and a “perfect” biological replica are not transferable material constants. For this stack, report VSET, current compliance, measured pulse width, switching probability, and E = ∫V(t)I(t)dt over statistically meaningful populations.
STP test
Apply isolated low-amplitude pulses, measure conductance decay from microseconds to seconds, fit more than one relaxation model, and verify spontaneous recovery over many devices.
LTP test
Apply controlled pulse trains at matched total energy, then measure retention, reversibility, state distributions, and whether the retained change comes from Ag, vacancies, or both.
STDP requires an additional paired-pulse experiment with controlled pre/post timing. Demonstrating STP and LTP separately does not by itself demonstrate a complete STDP learning rule or “total cognitive emulation.”
Criterion-by-criterion decision
CMOS integration: Cu–Te leads conditionally
Copper benefits from existing BEOL knowledge, barriers, and metrology. The lead is conditional because a CBRAM reservoir intentionally releases Cu ions, unlike a sealed interconnect; each foundry must approve the module.
Speed and low voltage: Ag–Te baseline
Silver is the leading fast-path hypothesis because Ag-based ECM commonly switches rapidly at low voltage. Device-level energy still requires measured current and pulse width.
Filament quality: no universal winner
Cu may form more stable or controllable filaments in some electrolytes, while Ag may better support volatility. Distributions of SET/RESET, retention, analog update, and endurance decide the winner.
Recommended down-selection: use Au as the nominally inert VCM control; retain Ag–Te as the fast reference; fabricate Cu–Te as the industrial alternative; test AgCu–Te as a controlled composition series; and keep Li as a distinct insertion channel. Compare all variants at identical geometry, matrix composition, compliance current, pulse energy, temperature, and sample size.
Comparison of major artificial-synapse technologies
| Technology type | State variable | Analog potential | Typical advantage | Central limitation | Cryogenic status |
|---|---|---|---|---|---|
| VCM oxide RRAM | Oxygen-vacancy distribution | Moderate to high with pulse control | Compact, mature CMOS research base | Forming and filament variability | Some devices demonstrated at low temperature; material-dependent |
| ECM / CBRAM | Ag or Cu metallic filament | Moderate; volatile and non-volatile modes | Low voltage and fast switching | Metal diffusion and abrupt filament growth | Must be measured for each electrolyte |
| Ion-intercalation / ECRAM | Distributed ionic concentration | High potential for gradual symmetric updates | Decoupled write/read in three-terminal forms | Speed, retention, electrolyte integration | Transport generally slows; no universal 4 K capability |
| Phase-change memory | Amorphous/crystalline fraction | High multilevel capability | Fast, scalable, established arrays | Write heat, drift, update asymmetry | Read possible; write physics needs cryogenic validation |
| Ferroelectric synapse | Polarization/domain configuration | High in multi-domain devices | Fast, non-volatile, low static power | Imprint, fatigue, device spread | Several devices retain function cryogenically |
| Magnetic / spintronic | Magnetization or domain texture | Moderate; often pulse-count based | High endurance and non-volatility | Write current, area, peripheral complexity | Often compatible with low temperature; device-dependent |
| Electrochemical transistor | Bulk ionic/electronic doping | High and often linear | Large dynamic range and biointerface compatibility | Footprint, speed, electrolyte stability | Usually not intended for 4 K |
| Proposed Ag⁺/Li⁺ co-ionic cell | Filament + insertion + vacancies | Potentially combines fast STP and gradual LTP | Multiple physical timescales in one cell | Pathway interference, control complexity, no measured device yet | 4 K operation is an explicit test target |
9Vertical Cell Architecture
The synaptic cell is a four-layer stack designed for 3D crossbar integration in the back-end-of-line (BEOL), deposited below 400 °C directly above the CMOS periphery.
Top ElectrodeDendritic fan-in connection · routes spike events to the reservoir
(Ag,Li)-Te ReservoirProposed buffered ionic supply layer · Ag⁺/Li⁺ release and diffusion barriers require measurement
(Ho,Sc,Ca)₂(S,F)₃ MatrixCandidate switching medium · proposed filament bias, candidate insertion sites, and anion-defect population to be measured
Bottom ElectrodeAxonal CMOS interface · 1T1R selector transistor, current compliance, sense circuitry
10Physical AI Architecture: Cell to 3D Processor
Architecture statusThe crossbar, selector, CMOS-periphery, and packaging concepts below are established engineering patterns. Their implementation with the proposed (Ag,Li)-Te / (Ho,Sc,Ca)₂(S,F)₃ stack remains a development program requiring process qualification.
Individual synaptic cell
The basic test structure is a two-terminal vertical device often described as metal–insulator–metal (MIM). Because the active layer is intentionally ion-conducting, metal–switching-medium–metal is the more precise description. From bottom to top, the proposed cell contains:
Bottom electrodeInert reference electrode and electrical connection to the selector or lower word/bit line
Switching matrix(Ho,Sc,Ca)₂(S,F)₃ thin film; target location for vacancy motion and Li⁺-associated conductance modulation
Ionic reservoir(Ag,Li)-Te thin film; proposed source and buffer for field-driven Ag⁺ and Li⁺ transport
Top electrodeUpper crossbar line; material and diffusion barrier must be selected experimentally
Under an electric field, ions are proposed to move mainly through the film thickness, changing junction conductance. Polarity, dominant carrier, filament geometry, pulse threshold, and reversibility must be established from control cells rather than assumed from the layer sequence.
Dimensions and density budget
A 10–20 nm lateral active junction can be treated as a scaling target, not the current device dimension. It does not imply a 10–20 nm array pitch: electrodes, selector footprint, overlay tolerance, vias, isolation, and routing enlarge the system cell. The stated density of 10¹⁰ cells/cm² corresponds to a 100 nm square pitch per layer. Vertical stacking can increase areal density, but each added plane also adds alignment, resistance, thermal, and yield constraints.
\[\mathrm{Pitch}=\frac{1}{\sqrt{10^{10}\,\mathrm{cm}^{-2}}}=10^{-5}\,\mathrm{cm}=100\,\mathrm{nm}\]
Crossbar operation
At each word-line/bit-line intersection, conductance Gij represents a synaptic weight. Applied row voltages produce column currents that approximate an analog matrix–vector multiplication through Ohm’s and Kirchhoff’s laws:
\[I_j=\sum_i G_{ij}V_i\]
This parallel operation is a valid basis for in-memory AI acceleration, but a practical tile also needs programming drivers, integrators, ADCs, calibration, signed-weight encoding, fault mapping, and digital control. Systematic crossbar error includes row/column IR drop, voltage-dependent device conductance, source/sense impedance, half-select leakage and sneak paths; stochastic error includes device variation, noise and drift. Array-size sweeps and a calibrated nodal or SPICE model must compare the realized column current with the ideal sum before assigning effective precision.
1T1R
One transistor per resistive cell provides strong current compliance and precise selection. It is suitable for early prototypes but constrains density because the access transistor and contacts commonly set a multi-F² footprint rather than the crosspoint alone.
1S1R
One nonlinear selector per resistive cell can approach the crosspoint footprint and support denser stacked arrays. Values such as roughly 6F² for compact transistor-selected layouts versus roughly 1–4F² for idealized selector/crosspoint layouts are technology-dependent planning references, not universal cell areas; contacts, isolation, overlay and routing must be included.
Monolithic CMOS and BEOL integration
The defensible processor topology places CMOS neuron and peripheral circuits below one or more memory planes. This shortens data paths compared with separate memory and compute chips. “Monolithic 3D” is achieved only after demonstrating that every post-CMOS deposition, etch, clean, and anneal respects the selected foundry’s thermal and contamination budgets.
1 · CMOS baseDrivers, selectors, ADCs, control, test access
2 · InterconnectPlanarization, vias, bottom lines, diffusion barriers
3 · Memory stackMatrix, reservoir, top lines, patterning
4 · QualificationYield, variability, contamination, thermal cycling
A nominal <400 °C deposition target is necessary but not sufficient. Silver, lithium, tellurium, sulfur, fluorine, and rare-earth cross-contamination rules, chamber dedication, outgassing, etch residues, and barrier integrity must be accepted by a specific process line. Compatibility cannot be claimed for TSMC, Samsung, IBM, or “any advanced foundry” without a process-design kit and foundry qualification.
Packaging is application-specific
| Deployment | Packaging priorities | Required qualification |
|---|---|---|
| Edge / industrial AI | Low-cost flip-chip or advanced package, thermal path, power delivery, sensor interfaces | JEDEC reliability, board-level thermal and signal-integrity tests |
| Aerospace | Hermeticity as required, low-outgassing materials, radiation-aware control electronics, thermal-cycle tolerance | Total-ionizing-dose and single-event testing at device and packaged-system levels; vibration and thermal-vacuum tests |
| Cryogenic / quantum control | Low thermal load, matched expansion, cryogenic interconnects, limited heat conduction into the cold stage | Electrical characterization across cooldown cycles and direct measurement of power dissipated at each temperature stage |
No single package is automatically optimal for aerospace and quantum systems: the first emphasizes radiation, vibration, and thermal-vacuum survival, while the second emphasizes heat load, cryogenic materials behavior, and wiring density.
AI scope
The credible near-term product is a neuromorphic or analog in-memory accelerator for inference and constrained adaptation. Biological connectivity motivates dense fan-in, but “brain-on-a-chip,” a definitive AGI processor, and equivalence to the human brain are not engineering specifications and are not supported by the current material or architecture evidence.
Evidence-bounded AI advantages by generation family
AI advantage boundaryAn advantage exists only when a complete workload improves at matched accuracy, model, duty cycle and reliability after drivers, ADCs, calibration, communication, idle power and host fallbacks are included. Device voltage, density or material novelty alone is not an AI advantage.
| Potential AI advantage | Most relevant generations | Mechanism or architectural basis | Best-fit workloads | System metric to improve | Boundary / fallback |
|---|---|---|---|---|---|
| Weight locality and reduced data movement | G1/G2, G8, G12–G16, G22 | Store conductance weights inside or directly above the matrix–vector fabric. | Dense inference, sparse linear layers, associative lookup and repeated sensor models. | Task energy, latency and memory traffic at matched accuracy. | Use SRAM/DRAM plus NPU when conversion, calibration or write cost dominates. |
| Parallel analog accumulation | G1/G2 controls; G12–G16 candidates | Column currents physically sum products of applied voltages and programmed conductances. | Matrix–vector kernels, correlation, filtering and approximate linear algebra. | Throughput per watt, residual error, effective precision and thermal load. | Keep numerically sensitive reductions and high-precision operations on CPU/GPU/NPU. |
| Event sparsity and early filtering | G4, G7–G9 | Volatile state, threshold selection and optical event input can suppress inactive or isolated events. | Event vision, acoustic bursts, vibration monitoring and wake-up sensing. | Events transmitted, false-alarm rate, end-to-end latency and active energy. | Use digital thresholding when selector heat, dark current or stochastic drift erases the saving. |
| Device-resident temporal context | G4, G17, G19, G21 | Candidate volatile and retained physical states represent fast transients and slower history without storing every timestep in an external digital recurrent-state buffer. This does not imply clockless operation or elimination of timing/control circuits. | Predictive maintenance, gesture/event sequences, biosignal adaptation and anomaly detection. | Sequence accuracy, state traffic, adaptation time and task energy–delay. | Revert to G19 paired cells or digital recurrent state if G21 pathways cannot be separated. |
| Lower calibration and initialization burden | G2, G14, G16 | Interface, dopant and compensation control target tighter distributions or first-cycle operation. | Precision analog inference, field calibration and frequently replaced sensor modules. | Good-die yield, verify pulses, guard bands, startup energy and recalibration frequency. | Use G1 with verify-write, redundancy and software calibration until distributions prove an improvement. |
| Long-lived edge adaptation | G11, G15, G16 | Barrier, passivation and compensated-host branches target environmental stability. | Remote infrastructure, industrial sensing and research systems under humidity or thermal cycling. | Uptime, drift, service interval and retained task accuracy after declared stress. | Package a CommercialStack core conventionally when material-level resilience is not demonstrated. |
| Higher local model capacity | G22 | Multiple selector-integrated memory planes increase geometric weight storage near compute. | Associative search, sparse inference and larger fixed edge models. | Usable weights per package, compound yield, thermal stability and task energy. | Use one plane or bonded 2.5D chiplets if vertical yield or IR drop dominates. |
| Multimodal in-sensor adaptation | G9, G23, G24 | Separately qualified optical or spin transducers can feed local temporal memory without a full raw-data round trip. | Scientific imaging, magnetic-event sensing and specialized remote instruments. | Information gained per joule, source-to-decision latency, loss, noise and accuracy. | Use commercial sensors plus an electrical G19/G21 core unless the transducer adds unique measured value. |
Processor execution model: CPU, APU, TPU, NPU and 3D acceleration
Processor boundaryOMNI is a proposed heterogeneous accelerator, not a drop-in replacement for an x86/Arm CPU, a commercial APU, TPU or NPU. A host CPU remains responsible for the operating system, memory protection, compilation, scheduling and precise control flow. Every accelerated function below is a supported design target until measured on a selector-integrated tile.
CPU hostCompiles graphs, schedules kernels, handles branches, exceptions, security and exact scalar arithmetic
APU-class packageUses the AMD-coined APU model of integrated CPU and GPU-class acceleration as a packaging analogy; OMNI is not an AMD APU
TPU / NPU baselineA TPU is Google’s tensor-oriented accelerator family; NPU is the generic neural-processor category. Both are separate digital baselines for tensor and inference workloads.
3D OMNI tileStores synaptic weights in memory cells; temporal state may occupy the same co-ionic cell only if separable, otherwise paired G19 cells or CMOS state are used
Binary
Use verified HRS/LRS distributions for robust Boolean decisions, sparse masks, threshold events and fallback inference. Binary mode is preferred when drift or noise destroys multilevel separation.
Ternary / trinary
Represent −1, 0 and +1 with a differential pair, a sign device plus zero gate, or three statistically separated conductance windows. A single cell is not called ternary until all three states meet retention and error-rate limits.
Analog multilevel
Use calibrated conductance for matrix–vector multiplication and learning. The 10-bit figure remains a target; effective precision is limited by noise, ADC ENOB, drift, nonlinearity and update statistics.
Host-visible command profile
OMNI should expose a compact accelerator command queue rather than claim native x86, Arm or RISC-V instruction execution. The names CONFIG_TILE, LOAD_WEIGHT, MVM, ACCUMULATE, THRESHOLD, ROUTE_SPIKE, UPDATE_PULSE, VERIFY, CALIBRATE and READ_STATE are a proposed internal API, not an implemented or standardized ISA. They must be mapped against existing execution models such as Intel Loihi/Lava, BrainChip Akida and IBM TrueNorth/NorthPole at the graph, event-routing, learning and state-management levels; binary compatibility is neither assumed nor required. Precise transcendental functions, control-heavy code and unsupported datatypes fall back to the CPU or conventional vector engine.
Processor and workload support maparchitecture targets
Qualitative role assignment, not a throughput benchmark. “Native target” means a proposed OMNI-tile primitive; “host” means CPU or conventional accelerator responsibility.
OMNI kernel profile and domain acceleration
OMNI kernel profile means only the subset of BLAS-like level-2 matrix–vector, sparse accumulation, threshold/event and low-order stencil operations that can be lowered to measured tile primitives. It is not a replacement for BLAS or LAPACK: factorization, pivoting, orthogonalization, high-precision reductions, exact division and nonlinear functions remain CPU/GPU operations unless a verified digital unit is provided. Every claimed kernel must report datatype, dimensions, sparsity, residual/error and data-conversion cost.
Chemical-numerics benchmark target
Use concrete encoded benchmarks rather than a general “chemistry acceleration” claim: for example, batched spectra with declared channel count, sparse Jacobian–vector products for reaction networks with 256 and 1,024 species, or fixed-grid diffusion/reaction stencil updates. Compare the same datatype and tolerance against a CPU BLAS/sparse solver and a GPU library, reporting residual, mass/conservation error, uncertainty, conversion energy and end-to-end latency. Device ion motion is not itself a chemistry solver.
Fast biological-computation target
Event filtering, biosignal feature extraction, spiking inference, temporal anomaly detection and adaptive sensor calibration fit the proposed STP/LTP timescales. “Biological” describes workload and inspiration, not living computation or brain equivalence; validate sensitivity, specificity, latency and energy on governed datasets.
\[\mathbf y=\mathbf G\mathbf v,\qquad \mathbf z_{k+1}=\mathcal Q\!\left(\mathbf A\mathbf z_k+\mathbf B\mathbf u_k\right),\qquad \mathcal Q\in\{\mathrm{binary},\mathrm{ternary},\mathrm{multilevel}\}\]
11Performance Benchmarks
These charts compare nine selected material modules: G1, G4, G10, G12, G14, G15, G16, G21 and G24. G1 is a literature-informed planning reference to reproduce locally; all other numerical values are illustrative engineering targets until measured on the named stack.
Not a complete generation rankingG2–G24 modules without matched voltage, energy, temperature, linearity, endurance or retention specifications are excluded. Material price and the five taxonomy planning indices are not used as performance proxies.
Switching voltage (V)selected-module targets
Illustrative targets. Forming-free operation would remove a separate electroforming step only if demonstrated statistically.
Energy per device update (pJ, log scale)selected-module targets
Illustrative device-level targets exclude selectors and periphery. G24 shows its ionic-core target; full optical/spin system energy is undetermined.
Operating-temperature test range (K, log)selected-module targets
All non-G1 ranges are planned qualification envelopes. The 4 K and 450 K endpoints are not demonstrated operating limits.
LTP/LTD update linearityselected-module targets
Quasi-linear, symmetric updates maximize effective analog states and training accuracy.
Endurance gate (cycles, log scale)selected-module targets
G1 uses a conservative 10⁶-cycle local reproduction gate, not a literature ceiling; HfOx reports can reach ≥10⁹ cycles in other stacks and protocols.
Retention stress projection at 200 °CAccelerated stress
The 200 °C curve is an illustrative accelerated stress beyond the 150 °C retention target, not measured data. Extrapolation requires a validated failure mechanism and confidence bounds.
Multi-criteria radar — selected modulesillustrative targets
Illustrative scores normalized 0–10 across eight engineering axes. They are hypotheses, not a complete G1–G24 ranking.
12Cross-Generation Comparison Standard
Single source of truthThe exhaustive G1–G24 comparison is the canonical matrix in the next section. Selected-module charts above do not redefine the taxonomy.
Every generation is compared using the same planning fields and evidence boundary. A higher generation number means lower estimated design ease and more dependencies, not better measured performance.
| Comparison axis | Required normalization | Invalid shortcut |
|---|---|---|
| Electrical | Same active area, thickness, electrodes, compliance, waveform, read voltage, temperature, and bandwidth | Comparing isolated best-device voltages or currents from unrelated stacks |
| Analog plasticity | Same update algorithm; report dynamic range, nonlinearity, asymmetry, noise, drift, and separable levels | Equating programming-pulse count with effective bit depth |
| Temporal dynamics | Same observation window and pulse energy; report decay/retention distributions and model uncertainty | Assigning STP or LTP from material chemistry alone |
| Reliability | Same failure definition, duty cycle, environment, censoring method, sample count, and confidence interval | Comparing a target with a literature maximum or extrapolating across changed mechanisms |
| Energy and latency | Integrate waveforms and include selectors, drivers, ADCs, transducers, control, and idle power at task level | Using voltage alone or excluding G24 optical/spin conversion overhead |
| Manufacturability | Compare thermal budget, contamination, uniformity, yield, tool dedication, packaging, and suppliers | Calling a material drop-in because one electrode metal is foundry-familiar |
| Evidence status | Separate established platform, cited precedent, measured local result, hypothesis, target, and frontier concept | Applying “BEST” labels before matched statistical experiments |
13Neuromorphic Generations G1–G24 Ranked by Design Ease
Canonical taxonomyG1–G24 is the sole generation structure used by the program. The order runs from the easiest controlled device to the most dependent frontier system. Percentages are relative planning indices, not measured performance, TRL, probability of success or product completion.
Ease estimates how directly a controlled prototype can be designed. Scientific advancement estimates novelty beyond established RRAM. Speed potential ranks plausible device response before peripheral overhead. CMOS maturity ranks process familiarity. Complexity rises with coupled materials, modules and validation dependencies.
Strict ordering ruleFrom G1 to G24, design ease must decrease and integration complexity must increase. Higher G does not mean better performance: it means more materials, interfaces, dependencies or proof gates must be closed before fabrication and system use.
G1–G4 · BaselinesSingle established oxide or ECM device families with direct control structures.
G5–G9 · One added functionDopant, selector or optical module added to a qualified baseline.
G10–G14 · New material systemSulfide host, barriers, reservoirs and occupancy-controlled dopant studies.
G15–G18 · Coupled chemistryPassivation, compensation, insertion or mixed active-metal composition.
G19–G21 · Compound temporal stateMultiple devices or coupled ions must preserve separable fast and retained behavior.
G22–G24 · System integration3D yield, transducers, bonding and end-to-end system evidence dominate difficulty.
| Generation | Module | Reference architecture | Ease | Scientific advancement | Speed potential | CMOS maturity | Complexity | Pros | Cons | Exit gate |
|---|---|---|---|---|---|---|---|---|---|---|
| G1 | HfOx VCM reference | TiN / HfOx / inert electrode, 1T1R | 92% | 25% | 70% | 90% | 18% | Mature ALD, metrology and compact models. | Forming, drift and asymmetric analog updates. | Reproduce binary and gradual states with full distributions. |
| G2 | HfOx/Al2O3 interface | TiN / Al2O3 / HfOx / inert electrode | 84% | 35% | 68% | 85% | 26% | Better oxygen-exchange and leakage control. | Added barrier may raise voltage and variability. | Beat G1 yield or retention at matched update quality. |
| G3 | Cu ECM reference | Cu / qualified solid electrolyte / inert electrode | 79% | 38% | 88% | 78% | 32% | Fast ECM with mature Cu process knowledge. | Mobile-Cu contamination and filament drift. | Repeatable charge-limited switching across three runs. |
| G4 | Ag ECM reference | Ag / qualified solid electrolyte / inert electrode | 77% | 42% | 94% | 62% | 35% | Very fast, low-voltage active-metal switching. | Abrupt SET, dendrites and Ag contamination. | Bounded volatile and retained distributions with Ag attribution. |
| G5 | Cr-doped HfOx | TiN / HfOx:Cr / inert electrode | 72% | 48% | 72% | 74% | 40% | Independent trap/redox tuning branch. | Leakage, secondary phases and dose sensitivity. | Beat undoped G1 across three deposition runs. |
| G6 | Mn-doped HfOx | TiN / HfOx:Mn / inert electrode | 69% | 52% | 70% | 72% | 43% | Polaron/trap tuning for gradual updates. | Valence complexity and process variability. | Beat G1 and G5 without retention penalty. |
| G7 | VO2 threshold selector | Memory cell + VO2 selector | 66% | 50% | 90% | 60% | 48% | Strong nonlinear threshold response. | Thermal sensitivity and transition spread. | Array margin improves after selector heating cost. |
| G8 | NbO2 threshold selector | Memory cell + NbO2 selector | 63% | 55% | 92% | 58% | 52% | High-temperature threshold-selector potential. | Stoichiometry, hold current and self-heating. | Endurance and array margin beat G7 or 1T1R. |
| G9 | ITO/ZnO optical module | ITO / ZnO sensor or modulator tile | 60% | 58% | 82% | 64% | 55% | Transparent sensing and optical event input. | Indium supply, optical loss and sputter damage. | Qualified optical signal before memory integration. |
| G10 | Undoped Ho₂S₃ host | Pt / Ho₂S₃ / Pt | 54% | 62% | 58% | 38% | 58% | Clean rare-earth-sulfide mechanism baseline. | Unproven switching, sulfur loss and oxidation. | Phase-pure film with attributed pulse switching. |
| G11 | Al₂O₃/SiO₂ encapsulation | Qualified cell + conformal barrier and isolation | 52% | 45% | 55% | 76% | 60% | Improved diffusion and environmental control. | Stress, pinholes and blocked ionic response. | Ageing improves without switching-energy penalty. |
| G12 | Ag–Te buffered reservoir | Ag–Te / qualified host / inert electrode | 49% | 68% | 88% | 42% | 64% | Potentially meters rapid Ag delivery. | Te scarcity, phase drift and interdiffusion. | Wider update window than G4 at equal charge. |
| G13 | Cu–Te buffered reservoir | Cu–Te / qualified host / inert electrode | 47% | 65% | 84% | 52% | 65% | Industrial Cu alternative with tunable activity. | Unproven release law and Te phase control. | Beat G3 in control or retention without energy penalty. |
| G14 | Sc-doped Ho₂S₃ | Pt / Ho2−xScxS₃ / Pt | 43% | 72% | 60% | 32% | 69% | Tests local-strain and defect-energy control. | Solubility, clustering and specialty precursors. | Measured Sc occupancy and improvement over G10. |
| G15 | Fluorosulfide host | Ag–Te / (Ho,Sc)₂(S,F)₃ / Pt | 38% | 76% | 62% | 28% | 73% | Passivation and harsh-environment hypothesis. | F may suppress switching or create new phases. | Stability improves while plasticity is preserved. |
| G16 | Ca/F compensated host | Ag–Te / (Ho,Sc,Ca)₂(S,F)₃ / Pt | 34% | 80% | 64% | 24% | 77% | Rational forming-free defect engineering. | Narrow composition window and leakage risk. | First-cycle yield beats G15 at matched retention. |
| G17 | Li insertion device | Li source / ion conductor / insertion host | 31% | 74% | 48% | 30% | 79% | Distributed gradual retained-state potential. | Trapping, plating and slow kinetics. | Reversible insertion chemically linked to conductance. |
| G18 | AgCu–Te reservoir | AgCu–Te / qualified host / inert electrode | 28% | 82% | 86% | 26% | 82% | Potential Ag-speed/Cu-control compromise. | Segregation and difficult causal attribution. | Beat both G12 and G13 within a bounded composition series. |
| G19 | Paired Ag/Li synapse | Volatile Ag cell + retained Li cell / CMOS neuron | 26% | 84% | 78% | 35% | 84% | Independent fast and slow state control. | Area, routing and peripheral-energy overhead. | Temporal-task gain survives full-system accounting. |
| G20 | Active Au ECM experiment | Au / selected electrolyte / TiN | 22% | 70% | 72% | 18% | 87% | Premium stability hypothesis and strong control value. | Au ionization uncertain; extreme tooling cost. | Direct reversible Au transport beats Ag/Cu on a stated metric. |
| G21 | Single-cell (Ag,Li)–Te synapse | (Ag,Li)–Te / compensated fluorosulfide / Pt | 17% | 91% | 82% | 14% | 91% | Compact native STP/LTP possibility. | Coupled pathways, drift and irreversible chemistry. | Ag, Li and host states are independently attributable. |
| G22 | Selected 3D crossbar | Multiple selector-integrated memory planes | 13% | 88% | 90% | 20% | 94% | High density and reduced data movement. | Compound yield, heat, vias and IR drop. | Two functional planes show task-level benefit. |
| G23 | Bi₂Te₃ spin/topological interface | Bonded Bi₂Te₃ transducer + electrical memory core | 9% | 95% | 86% | 10% | 96% | Potential unique spin/charge transduction. | Fermi-level control, oxidation and interface loss. | Measured transduction link beats electrical baseline. |
| G24 | Complete spin–opto–ionic OMNI | G21/G22 memory + G9 optical + G23 spin modules | 4% | 100% | 88% | 5% | 100% | Unified sensing, memory, communication and adaptation. | Highest loss, yield, control and qualification burden. | End-to-end unique function or energy–delay gain. |
Key architectural fallbackG21 does not need every timescale inside one physical cell. If Ag and Li cannot be independently controlled, use the G19 paired-cell architecture. This preserves fast/slow neuromorphic behavior while isolating materials and programming paths.
Candidate inventions and usable processor concepts for every generation
Invention boundaryEach row is a product or research concept enabled by the named generation if its exit gate is met. These are not demonstrated products, patentability opinions, market forecasts or measured advantages. A generation may be useful as a control, sensor, memory, selector or transducer without becoming a complete standalone processor.
| Generation | Candidate invention | How it could be used | Why this generation fits | Proof before use | Fallback |
|---|---|---|---|---|---|
| G1 | Nonvolatile calibration and trim engine | Retain sensor offsets, motor-control gains or analog front-end correction tables near the controller. | HfOx offers the most mature local VCM reference and a practical 1T1R control path. | Retention, write energy, drift and error rate must beat embedded Flash or digital trim for the named duty cycle. | Conventional NVM plus digital calibration. |
| G2 | Low-leakage adaptive calibration register | Store slowly updated factory or field calibration with reduced read disturb and bounded oxygen exchange. | The Al2O3 interface is intended to constrain leakage and first-cycle variability. | Yield or retention must improve over G1 at equal update quality and full-cell energy. | G1 with verify-write and stronger error correction. |
| G3 | Cu-ECM stochastic entropy cell | Generate device-level random events for probabilistic sampling, challenge-response research or randomized learning. | Charge-limited Cu filament nucleation may provide measurable switching stochasticity. | Bias, autocorrelation, temperature dependence, ageing and attack resistance require independent statistical testing. | CMOS true-random source or deterministic pseudorandom generator. |
| G4 | Volatile event-decay filter | Suppress isolated sensor spikes while passing bursts in acoustic, vibration or event-camera streams. | Ag ECM can be tested for fast formation followed by spontaneous filament relaxation. | Decay distributions and task benefit must remain stable across devices, temperature and cycling. | Digital leaky integrator or capacitor-based analog filter. |
| G5 | Cr-tuned analog compensation cell | Learn a bounded correction curve for nonlinear sensors or analog actuator control. | Cr provides an independent trap/redox tuning branch for gradual HfOx updates. | G5 must beat G1 in linearity or variability across at least three runs without leakage or retention penalty. | Undoped G1 with algorithmic pulse shaping. |
| G6 | Mn-tuned adaptive threshold memory | Retain and update anomaly thresholds for always-on industrial sensing. | Mn-dependent polaron/trap behavior may support a distinct gradual-update window. | Threshold stability, multilevel separation and endurance must beat G1 and G5 under matched protocols. | Digital threshold register with periodic retraining. |
| G7 | VO2 spike gate and array protector | Block sub-threshold sneak current and emit a nonlinear access event for compact spiking arrays. | The threshold transition provides an explicit gating function rather than an additional memory state. | Selector heating, hold-current spread and lifetime must improve array margin after energy accounting. | Transistor selector or diode-selected array. |
| G8 | NbO2 threshold-addressed memory fabric | Address denser crossbar rows for associative lookup, sparse inference or event routing. | NbO2 is the higher-temperature threshold-selector branch with strong nonlinearity potential. | Array yield, leakage, half-select immunity and thermal cross-talk must beat G7 and 1T1R baselines. | G7 selector or conventional access transistor. |
| G9 | Transparent event-pixel preprocessor | Detect or modulate optical events at a window, display, microscope or image-sensor surface before digital transfer. | ITO/ZnO combines transparent conduction with a separately testable photoconductive response. | Responsivity, noise, optical loss and system energy must beat an external photodiode plus processor. | Commercial image sensor or silicon-photonic input. |
| G10 | Rare-earth sulfide defect-analysis chip | Map pulse-dependent sulfur-defect, trap and interface signatures for materials discovery and sensor research. | Undoped Ho₂S₃ isolates the host before reservoirs or dopants are introduced. | Phase-pure films and chemically attributed switching are required before any compute claim. | Use G10 only as a material coupon; retain G1 for computation. |
| G11 | Self-monitoring hermetic memory package | Protect adaptive memory in humid, corrosive or thermally cycled equipment while tracking barrier degradation. | Al2O3/SiO2 adds explicit diffusion, passivation and isolation functions. | Accelerated ageing must improve without blocking switching or increasing total update energy. | Package-level hermetic seal around a G1 module. |
| G12 | Charge-metered analog learning engine | Program smoother weights for calibration-efficient inference, adaptive filters or edge learning. | An Ag–Te reservoir may meter Ag delivery and reduce filament overshoot relative to G4. | The usable update window must widen without worse leakage, retention, endurance or energy. | G4 with strict current compliance and verify-write. |
| G13 | Cu-compatible temporal learning macro | Implement low-volume temporal filters using a reservoir chemistry closer to industrial Cu handling. | Cu–Te tests controlled Cu activity while retaining a conventional Cu comparison route. | Release law, contamination boundary and update control must beat pure-Cu G3. | G3 Cu ECM or bonded G12 specialty module. |
| G14 | Self-calibrating precision weight array | Reduce guard bands and recalibration in metrology, scientific instruments or high-value analog inference. | Sc occupancy is tested as a composition-linked route to narrower defect and conductance distributions. | Blind multi-run statistics must show lower variability than G10 without an energy or lifetime penalty. | G1/G10 arrays with digital calibration and spare-cell mapping. |
| G15 | Environmentally resilient remote-sensor memory | Retain adaptive state in remote infrastructure, industrial monitoring or aerospace research payloads. | The fluorosulfide branch explicitly tests passivation and environmental stability. | Humidity, oxidation and thermal-cycle survival must improve while plasticity remains measurable; radiation requires separate tests. | G11 encapsulated oxide memory. |
| G16 | Factory-initialization-free adaptive controller | Reduce high-voltage forming, wafer screening and field initialization in adaptive sensor or actuator modules. | Ca/F compensation is designed to tune the initial defect population and first-cycle behavior. | First-cycle yield and energy must beat G15 at matched leakage, retention and endurance. | Pre-formed G15 or G1 with controlled factory initialization. |
| G17 | Cumulative exposure and history integrator | Encode slowly accumulated vibration, chemical exposure, usage or calibration history as an analog state. | Reversible Li insertion is a candidate distributed, retained state variable. | Coulometry and spectroscopy must separate insertion from plating, trapping and irreversible conversion. | Digital counter, electrochemical sensor or conventional ECRAM control. |
| G18 | Tunable-volatility dual-metal reservoir | Adjust forgetting time or update abruptness for workload-specific temporal filters. | AgCu–Te provides a controlled composition axis between Ag speed and Cu retention/control hypotheses. | A bounded composition series must beat both G12 and G13 and attribute each metal flux. | Select either G12 or G13 rather than mixing reservoirs. |
| G19 | Dual-timescale predictive-maintenance node | Track fast transients and slow equipment degradation independently in one sensor module. | Separate volatile Ag and retained Li cells preserve mechanism independence under one CMOS neuron. | Task energy–delay and fault tolerance must beat a digital recurrent state and one-cell implementation. | Retained G1/G17 cell plus digital short-term buffer. |
| G20 | Noble-metal transport assay and tamper sensor | Use a tightly bounded Au transport experiment to detect irreversible interface disturbance or environmental exposure. | Au is valuable as a stringent inert-versus-active control and may migrate only in selected electrolytes. | Direct reversible Au transport and a unique signal over Ag/Cu and inert controls are mandatory. | Keep Au inert and use G3/G4 for ECM sensing. |
| G21 | Single-cell temporal-fusion engine | Perform burst detection, adaptation and retained context close to event sensors with fewer physical cells. | The co-ionic cell tests whether Ag and Li can encode separable fast and slow state variables. | Chemical attribution and task benefit must exceed paired-cell G19 after calibration and peripheral cost. | G19 paired-cell compound synapse. |
| G22 | Three-dimensional associative-search cube | Run dense nearest-pattern search, sparse inference or local model storage with reduced off-tile data movement. | Multiple selector-integrated planes provide the program's highest geometric density option. | At least two planes must show bounded vertical yield, heat, IR drop and task-level energy benefit. | One qualified plane or bonded 2.5D chiplets. |
| G23 | Spin-charge event router | Translate magnetic or spin-domain events into electrical memory updates for scientific sensing or cryogenic-control research. | Bi₂Te₃ is treated as a separately bonded spin/charge transducer, not as the memory itself. | Measured conversion, noise, interface loss and energy must beat a conventional electrical transducer. | Heavy-metal or semiconductor spin-orbit transducer. |
| G24 | Multimodal autonomous scientific instrument | Combine optical sensing, spin/magnetic input, temporal memory and local adaptation for remote experiments or specialized diagnostics. | G24 is the only architecture that intentionally joins G9 optical, G23 spin and G21/G22 memory modules. | A complete source-to-decision path must enable a unique function or beat the electrical G21/G22 baseline. | CommercialStack or electrical G21 with external sensors. |
Development portfolio and evidence-bounded sales case
Commercial ruleThe propositions below describe maximum credible customer value if each proof gate is met. They are not current product capabilities. G1–G8 are reference and control vehicles; differentiated options include G12, G14–G16, G19 and G21, while G24 is separately financed.
| Priority | Technology worth developing | Customer problem | Maximum credible benefits | Defensible differentiation | Best first market | Revenue path | Proof before selling |
|---|---|---|---|---|---|---|---|
| 1 · Flagship | G16 · Ca/F-Compensated Forming-Free Synapse | High-voltage electroforming increases test time, peripheral complexity, early failures, and array-yield loss. | Potential first-cycle operation; lower initialization energy; simpler high-voltage support; faster wafer test; improved usable-array yield; reduced screening and redundancy burden; safer field initialization. | Charge-compensated Ca/F/vacancy process window tied to composition, first-cycle statistics, and a transferable compact model. | Industrial edge, automotive/avionics research, radiation-screened electronics, and low-power adaptive sensor modules. | Process-module license, qualified die or chiplet, foundry transfer NRE, reliability characterization, and application-specific joint development. | First-cycle yield and update energy must beat G15 at matched geometry while retention, leakage, endurance, and variability remain within specification. |
| 2 · Flagship | G21 · Ag/Li Single-Cell Dual-Timescale Synapse | Conventional accelerators move temporal state between sensor, memory, and processor or emulate fast/slow dynamics with multiple devices and software. | Potential native STP and retained LTP/LTD; local temporal filtering; fewer state transfers; lower memory traffic; compact adaptive sensor nodes; event-driven learning; metaplasticity; reduced dependence on recurrent digital state; one-cell or tightly coupled fast/slow implementation. | Measured separation of Ag, Li, and host state variables plus a pulse protocol and compact model that preserve task-level gain after selector and peripheral energy. | Event vision, vibration/acoustic anomaly detection, robotics, biosignal adaptation, and always-on edge inference. | Premium temporal-processing chiplet, architecture/IP license, model and compiler enablement, evaluation modules, and workload-specific co-design. | A selector-integrated array must outperform G19 in task energy–delay at matched accuracy, lifetime, calibration, and duty cycle. |
| 3 · High | G12 · Ag–Te Buffered Analog Synapse | Abrupt active-metal filament growth produces narrow programming margins, write failures, excessive verify-write, and poor analog update control. | Potentially wider programming window; smoother incremental updates; lower overshoot and hard-short rate; fewer verify pulses; tunable volatility; improved effective bit depth; better training accuracy; longer useful endurance through moderated ion delivery. | Reservoir composition and thickness become controllable process knobs with chemical-depth evidence linking Ag delivery to electrical distributions. | Analog in-memory inference, calibration-efficient accelerators, temporal filters, and research macros requiring repeatable multilevel weights. | Reservoir-stack patent license, process recipe, material target/precursor specification, characterization service, and co-optimized memory macro. | G12 must widen the usable update window versus G4 without worsening leakage, retention, endurance, yield, or total programming energy. |
| 4 · High | G14 · Sc-Guided Analog Synapse | Device-to-device and cycle-to-cycle variability forces calibration, verify-write, guard bands, spare cells, and algorithmic retraining. | Potentially tighter conductance distributions; more reliable multilevel states; fewer calibration cycles; smaller guard bands; higher effective yield; improved inference repeatability; reduced compensation overhead; clearer process-control limits. | A composition-linked variability improvement supported by Sc occupancy, defect/strain evidence, mixed-effects statistics, and repeatable multi-run fabrication. | Metrology/reference wafers, precision analog memory, low-volume high-value accelerators, and licensed materials/process optimization. | Composition/process IP, qualified target or precursor specification, statistical process-control package, engineering wafers, and device-model licensing. | Pre-registered G14 distributions must beat G10 across at least three independent runs without leakage, retention, energy, or endurance penalty. |
| 5 · Niche premium | G15 · Fluorosulfide Resilient Synapse | Humidity, oxidation, temperature excursions, leakage drift, and mission environments can erase the economics of otherwise efficient analog memory. | Potentially improved environmental stability; lower leakage drift; broader qualification envelope; reduced recalibration; longer service intervals; less packaging dependence; premium reliability positioning; a controlled path to radiation testing. | Matched stress data linking F bonding/composition to survival while preserving plasticity, rather than relying on a generic “rad-hard” material claim. | Aerospace and defense research, industrial sensing, remote infrastructure, high-temperature monitoring, and long-life edge modules. | High-margin qualified components, environmental-screening data packages, mission-specific joint development, process licensing, and long-term supply agreements. | Humidity and thermal survival must improve over G12 at matched plasticity; radiation value requires separate TID/SEE evidence and package-level qualification. |
| 6 · Strategic option | G24 · Heterogeneous Spin–Opto–Ionic System | Electrical data movement and separate sensor, communication, memory, and compute stages dominate latency or energy in specialized systems. | Potential in-sensor adaptation; non-electrical broadcast; local event memory; reduced conversion and interconnect traffic; multimodal sensing; unique optical/spin interfaces; modular chiplet integration; access to mission-specific functions unavailable to a purely electrical core. | A measured transduction link or unique function that survives complete source-to-output energy, latency, loss, calibration, and compound-yield accounting. | Photonics-enabled sensing, scientific instruments, cryogenic research, secure/remote sensing, and mission-led demonstrators rather than commodity AI. | Consortium-funded demonstrator, strategic option license, transducer chiplet IP, sponsored research, and application-exclusive joint development. | Fund one transducer at a time; advance only when the complete path beats G21/G22 or enables a unique function. |
Lower customer cost
G12, G14 and G16 target fewer calibration/verify operations, lower screening burden, higher usable yield, and simpler initialization. These savings must be demonstrated in good-die cost and test-time data.
Higher product value
G15 can justify reliability premiums in harsh environments, while G19/G21 can support premium temporal-processing modules when they reduce measured task energy–delay or system memory traffic.
Stronger IP leverage
The most defensible package combines composition ranges, process windows, pulse protocols, compact models, qualification data, and workload evidence. A nominal formula alone is not a commercial moat.
Recommended capital sequence: fund G12 and G14 as parallel risk-reduction modules; advance G16 as the strongest materials-led product proposition; use G19 as the controlled dual-timescale fallback before G21; fund G15 through a named harsh-environment customer; and keep G24 outside the core budget until a partner finances a specific transduction milestone.
Neuromorphic proof gates shared by all generations
1 · StateSeparated conductance distributions, read-disturb limit, retention and reversibility
2 · PlasticityPotentiation/depression curves, dynamic range, asymmetry, nonlinearity and noise
3 · TimeSTP decay or LTP retention measured as distributions, not inferred from chemistry
4 · LearningPPF/STDP or task-relevant update rule demonstrated with energy-matched controls
5 · ArraySelector, half-select disturb, yield, drift compensation and task-level accuracy
A hysteretic I–V loop alone proves neither a synapse nor learning. G1 through G9 cover oxide, ECM, selector and optical controls; G10–G18 add sulfide, reservoir, compensation and insertion chemistry; G19–G21 test dual-timescale architectures; G22–G24 add 3D, spin and complete heterogeneous integration. Application fit, not generation number, determines value.
Implementation ease and dependency ladder
Program-planning estimate. A longer bar means easier to begin; it is not a device-performance score.
Calendar logic
2026 · G1–G4Qualify HfOx, interface-controlled VCM, and separate Cu/Ag ECM references.
2027–2028 · G5–G9Run Cr/Mn branches, qualify VO₂/NbO₂ selectors, and test the ITO/ZnO optical module.
2028–2031 · G10–G14Qualify Ho₂S₃, encapsulation, Ag–Te/Cu–Te reservoirs and the Sc composition series.
2030–2034 · G15–G19Test fluorosulfide, Ca/F compensation, Li insertion, mixed reservoirs and paired temporal cells.
2033–2038 · G20–G22Bound the Au experiment, demonstrate a co-ionic cell and then a selected 3D crossbar.
2037–2040+ · G23–G24Qualify Bi₂Te₃ transduction before integrating the complete spin–opto–ionic system.
14Industrial Bridge Roadmap: Lab to Foundry
Research and transfer viewsG1–G24 ranks design ease in the research program. I1.0 is reserved for the foundry-native oxide-RRAM/G1 baseline; I1.5 is the first novel oxysulfide transfer bridge between that baseline and I2.0. I1.5–I7 ranks transfer vehicles by industrial disruption. These labels are internal planning names, not TRLs, foundry approvals or guaranteed dates.
The industrial objective is not to ask a high-volume fab to accept the full co-ionic stack at once. Each bridge keeps a useful neuromorphic function while introducing one contamination class or process module at a time. Existing Cu/W-compatible tools can reduce capital needs, but no Ho–S–Te stack is automatically “drop-in”: dedicated chambers, barriers, cleans, wafer-edge exclusion, thermal budgets, and product-specific reliability still require qualification.
Phased transfer vehicles
Deliberate G↔I decouplingThe industrial bridges introduce one contamination or chemistry module at a time rather than copy the canonical G stack. I5 omits F to isolate Ca/vacancy compensation before the full G16 Ca/F composition; I6 retains the qualified F host but omits Ca to isolate Li before the full G21 co-ionic stack. Advancement requires controls against the matching canonical generation.
| Industrial rank | Indicative horizon | Bridge vehicle | Neuromorphic product | Why it is pragmatic | New fab risk | Exit gate / fallback |
|---|---|---|---|---|---|---|
| 1 · I1.5 | 1–2 years after funded start | Oxysulfide Bridge Cu / Ho₂O₂S / W | Binary or modest multilevel inference memory; pulse-programmed LTP/LTD with controller compensation | W is a robust electrode and Cu has mature barrier/metrology knowledge; oxygen can improve process familiarity and environmental stability versus a pure sulfide | Ho₂O₂S deposition, phase control, Cu ion release, sulfur contamination, etch residues | Demonstrate capped 1T1R cells below the selected BEOL thermal limit; fallback to HfOx/Ho-oxysulfide bilayer or external Cu reservoir |
| 2 · I2.0 | 1–3 years | Standard-Alloy Bridge Cu–Te / Ho₂S₃ / W | Low-voltage ECM/VCM weights and temporal filtering | Cu replaces Ag as the active metal and leverages existing Cu barrier expertise; Cu–Te may meter ion activity | Cu–Te phase variability, Te cross-contamination, sulfur loss, abrupt filaments | Pure-Cu and Cu–Te split lots must show a wider programming window; fallback to nanolaminate barrier or Cu nanoclusters |
| 3 · I3.0 | 3–5 years | Scandium Variability Test Cu–Te / Ho₂S₃:Sc / W | Test whether Sc measurably narrows D2D/C2C distributions and improves analog repeatability | Adds one controlled host variable after I2 is stable and may define a useful composition/process window | Sc target/precursor qualification, secondary phases, and no demonstrated deterministic path | Pre-registered statistical improvement over I2 across at least three deposition runs; otherwise retain x = 0 |
| 4 · I4.0 | 3–6 years | Fluorosulfide Resilience Cu–Te / F–Ho₂S₃:Sc / W | Environmentally stable analog memory for aerospace screening | Separates passivation and radiation-testing work from Ag/Li complexity | F chemistry, abatement, bonding uncertainty, mobility suppression; radiation hardness is not implied by fluorination | Matched humidity, thermal-cycle and TID tests must improve survival without degrading updates; fallback to encapsulation-only passivation |
| 5 · I5.0 | 5–8 years | Ca Forming-Free Synapse Ag–Te / (Ho,Sc,Ca)₂S₃ / W | Low-voltage analog adaptation with engineered initial defect populations | Introduces Ag and Ca only after host/reservoir learning; targets a differentiated low-energy niche | Ag contamination, Ca/vacancy compensation, leakage–retention trade-off, forming yield | Forming-free yield and energy must beat I4 at equal geometry; fallback to Cu–Te/Ca or controlled forming |
| 6 · I6.0 | 8–12 years | Quantum-Temperature Co-Ionic (Ag,Li)–Te / F–Ho₂S₃:Sc / W | Ag-mediated STP plus Li-mediated retained adaptation, including cryogenic research | Introduces Li only after the fast pathway and host are independently understood | Li contamination, low-temperature kinetics, Ag/Li interference, compact-model complexity | Ag-only, Li-only and combined controls must separate state variables; fallback to paired I4/I5 devices |
| 7 · I7.0 | 10+ years | OMNI System Demonstrator Electronic/ionic memory + separate spin and optical routing layers | Heterogeneous tile combining memory, event sensing, local learning and non-electrical communication | Tests each physical channel as a chiplet or bonded layer before attempting one monolithic material | Transduction loss, alignment, thermal cross-talk, incompatible process windows and system-control overhead | System energy and task accuracy must beat an electrical baseline including converters; fallback to photonic I/O around an I5/I6 ionic core |
Foundry acceptance gates
1 · Tool compatibilityPrecursor safety, chamber dedication, Cu/Ag/Li/Te/Ho cross-contamination and abatement
2 · IntegrationThermal budget, diffusion barriers, etch/clean, CMP, wafer edge and topography
3 · ManufacturabilityUniformity, defectivity, overlay, yield, metrology and statistical process control
4 · QualificationTDDB, retention, endurance, electromigration, package stress and application reliability
5 · Design enablementCompact model, PDK rules, variability corners, test structures, selector and peripheral IP
Using an already familiar metal does not approve a new device module. TSMC, Intel, Samsung, IBM, or any other manufacturer can be named only as a prospective qualification environment after a bilateral process review; this dossier makes no claim of acceptance by any foundry.
Valley-of-death operating plan
| Milestone | Deliverable | Customer-facing value | Kill criterion |
|---|---|---|---|
| 200 mm research module | I1.5 or I2 integrated above a selector-compatible wafer with full contamination log | Binary/multilevel inference macro, not a materials coupon | No reproducible array margin after two process-learning cycles |
| Niche demonstrator | I3/I4 packaged for high-temperature, radiation, sensor, or industrial-edge evaluation | A measured niche advantage unavailable from commodity RRAM | No system-level benefit after ADC/driver/package energy is included |
| Pilot line | Process-control plan, second material source, wafer maps, reliability distributions and compact model | Transferable module and design kit | Yield or lot variability cannot support agreed customer specification |
| Advanced platform | I5/I6 selector-integrated tile with hardware learning or temporal processing | Differentiated adaptation rather than only denser storage | Complex chemistry does not outperform a paired simpler-device solution |
13AG24 · NEURO-SYNAPSE-OMNI: Spin–Opto–Ionic Frontier
Exploratory architecture, not a product claimG24 is a research horizon beyond the G1–G23 device and module sequence. “OMNI,” “cognitive material,” zero-VDD operation, AGI relevance, and self-powered processing are hypotheses or metaphors until component- and system-level measurements exist. There is no scientifically defensible “final generation” beyond which computing cannot evolve.
Candidate heterostructure: Bi₂Te₃ opto/spin interface / (Ag,Li)–Te ionic reservoir / (Ho,Er,Sc,Ca)₂(S,F)₃ adaptive host. Writing this formula does not establish phase compatibility, band alignment, topological surface transport, magnetic order, optical gain, ion selectivity, or manufacturability. The first credible implementation should be heterogeneous: separately optimized ionic, magnetic, and photonic layers connected by measured transducers.
Three physical channels and one interface
| Channel | Defensible opportunity | What is not established | Required experiment | Fallback architecture |
|---|---|---|---|---|
| Ionic · local memory | Ag may provide volatile dynamics and Li may provide slower retained state changes | Independent, durable control of Ag, Li and vacancy populations in the G24 heterostructure | Factorial Ag-only/Li-only controls, operando transport/chemistry and retention/endurance distributions | Two-device fast/slow synapse under CMOS control |
| Spin · local routing | Ho³⁺ has a large 4f magnetic moment; spin waves can carry phase/frequency information with potentially low charge-current dissipation | Useful magnetic order, magnon propagation length, damping and electric/ionic transduction in Ho₂S₃-based films | Temperature- and field-dependent magnetometry, ferromagnetic resonance/Brillouin light scattering, patterned waveguides and transducer energy | Use a qualified YIG, ferrite, or metallic spin-wave layer bonded to the ionic memory |
| Optical · broadcast/modulation | Er can provide host-dependent near-infrared transitions; optical broadcast may deliver a global modulatory or reward signal | Optical activity after co-doping, efficient coupling, plasmonic benefit, weight-selective response, and net energy advantage | Photoluminescence lifetime, absorption, waveguide loss, modulation depth, cross-talk and learning-task comparison | External silicon-photonic/III–V source and waveguide over an ionic array |
| Topological interface | Bi₂Te₃ is a canonical topological-insulator material platform under suitable composition, thickness, Fermi level and interface conditions | Surface-dominated transport in the fabricated stack or useful spin-charge conversion after processing | Hall/weak-antilocalization/ARPES where available, thickness series, bulk-carrier suppression and spin-torque measurement | Conventional heavy-metal or semiconductor spin–orbit transducer |
Magnons are not “heat-free”: generation, damping, detection and conversion dissipate energy, and propagation is finite. Optical modulation is not instantaneous: latency is bounded by source, cavity/waveguide, detector and material response. A global optical reward signal may complement local learning, but it does not replace credit assignment or guarantee efficient backpropagation.
G24 chemistry that must be resolved before integration
| Chemical subsystem | Property that controls function | Principal competing mechanism | Required discriminating evidence | Go/no-go condition |
|---|---|---|---|---|
| Bi₂Te₃ native defects | Te vacancies, Bi/Te antisites, stoichiometry, dopants, thickness, and surface adsorbates can set carrier density, carrier type, and Fermi-level position. | Bulk carriers or defect bands can dominate the intended surface channel; oxidation, Te loss, disorder, or processing damage can erase the useful interface state. | Composition/thickness series combining XRD/TEM, XPS/UPS, Hall, temperature-dependent transport, weak antilocalization and ARPES where available. | Proceed only if the processed interface retains reproducible surface-relevant or useful spin-charge transport at the operating temperature. |
| Bi₂Te₃ chemical interfaces | Work functions, band offsets, interface dipoles, termination, adhesion, reaction energies, and spin transparency govern injection and transduction. | Ag, Li, S, F, oxygen, or electrode species may react or diffuse into Bi₂Te₃, forming a resistive, metallic, magnetic, optically lossy, or topologically trivial interphase. | Dedicated diffusion couples and capped stacks with depth-resolved XPS/SIMS, cross-sectional STEM-EELS/EDS, anneal/bias matrices, Kelvin probe/UPS, and interface resistance. | Use direct integration only when reaction products and diffusion remain within a declared thermal/bias budget; otherwise insert a qualified barrier or bond separate modules. |
| Er³⁺ site chemistry | Er site occupancy, coordination, oxidation state, ligand field, local symmetry, solubility, and charge compensation determine its absorption and emission spectrum. | Er-rich clusters or secondary phases, mixed valence, compensating defects, and interaction with Ag/Li pathways can create electrically or optically inactive centers. | Er concentration series with XRD/EXAFS or local probes, STEM-EDS, XPS, absorption/excitation spectra, and composition-correlated time-resolved photoluminescence. | Advance the host-doped option only if Er³⁺ incorporation is reproducible and produces a useful optical response without degrading the qualified G21 ionic-core switching or retention. |
| Er³⁺ concentration quenching | Mean Er–Er separation, energy migration, cross-relaxation, cooperative upconversion, and transfer to traps determine radiative efficiency at useful concentration. | Non-radiative multiphonon relaxation, defect/surface recombination, free-carrier absorption, and Er–Er energy transfer can shorten lifetime or extinguish emission. | Concentration-, temperature-, pump-power-, and time-resolved spectra separating radiative lifetime, non-radiative rate, quantum yield, upconversion, and waveguide propagation loss. | Select the concentration at maximum system modulation per source energy, not maximum Er content; use a separately optimized optical layer if the adaptive host quenches emission. |
| Cross-channel chemical coupling | Ag/Li motion and host-defect charging may shift bands, optical centers, magnetic exchange, or interface transparency and thereby enable or corrupt modulation. | Irreversible redox, ion trapping, screening, Joule heating, phase segregation, and interdiffusion can mimic a reversible optical or spin learning signal. | Factorial Ag-only, Li-only, Er-free, Bi₂Te₃-free, dark/illuminated, field/no-field and barrier controls with simultaneous electrical, optical, magnetic and chemical tracking. | Claim coupling only when a reversible chemical state predicts the transduced output across repeated devices and outperforms thermal/electrostatic artefact models. |
\[\frac{1}{\tau_{\mathrm{meas}}}=k_r+k_{nr}+k_{\mathrm{transfer}}([\mathrm{Er}],\,\mathrm{defects},\,\mathrm{interfaces},\,T)\]
The Er³⁺ lifetime equation is a measurement framework, not an assumption that any term is constant. Likewise, a Bi₂Te₃ composition label does not establish a surface-dominated channel: carrier compensation and the processed Fermi level must be demonstrated in the actual interface stack. Missing formation energies, migration barriers, activities, diffusion coefficients, phase equilibria, and band offsets remain DFT/thermodynamic or experimental deliverables.
In-sensor neuromorphic operation
A useful G24 in-sensor target combines a qualified G9 ITO/ZnO optical module with local ionic memory so that a pixel or event detector directly changes a local conductance or modulates a learning gate. This can remove some data conversion and movement, but the saving must be measured against dark current, illumination energy, optical coupling, calibration, readout and peripheral circuits. No fixed “90%” saving is assumed.
SensePhotocarrier or resonant optical absorption with wavelength/intensity calibration
GateOptical or spin signal changes ionic programming probability, not the read current alone
StoreAg/Li/vacancy state retains a local feature or adaptation parameter
ComputeArray current, optical interference, or spin-wave response produces a task output
Energy and latency accounting
\[E_{\mathrm{event}}=E_{\mathrm{source}}+E_{\mathrm{transducer}}+E_{\mathrm{propagation\ loss}}+E_{\mathrm{write}}+E_{\mathrm{read}}+E_{\mathrm{periphery}}\]
\[\eta_{\mathrm{harvest}\rightarrow\mathrm{compute}}=\frac{P_{\mathrm{useful\ compute}}}{P_{\mathrm{ambient\ captured}}},\qquad D\leq\frac{P_{\mathrm{harvest,avg}}}{P_{\mathrm{active}}}\]
Tribo-, thermo-, photovoltaic, vibration, or RF harvesting can support intermittent sensing when average harvested power exceeds sleep, leakage, storage and duty-cycled compute demand. It does not create energy. “Zero-VDD” should mean no continuous external supply under a specified ambient source and duty cycle, not zero energy consumption or autonomous operation under all conditions.
G24 fabrication and machine additions
| Module | Additional capability | Critical measurement | Development blocker |
|---|---|---|---|
| Bi₂Te₃ interface | MBE or qualified sputter/PLD growth, inert transfer, low-damage patterning | Stoichiometry, crystalline texture, carrier density/mobility and interface chemistry | Bulk conduction and process-induced surface degradation |
| Magnetic/spin layer | Vector magnet, cryostat, VSM/SQUID, FMR or Brillouin-light-scattering access | Damping α, propagation length, dispersion, switching/transduction energy | Ho compound may not provide a useful room-temperature magnonic medium |
| Er optical module | Tunable laser, spectrometer, time-resolved photoluminescence, waveguide/probe alignment | Absorption/emission, lifetime, quantum efficiency, modulation and cross-talk | Concentration quenching and optical loss in the complete host |
| Heterogeneous integration | Wafer bonding or transfer printing, alignment, planarization and thermal-stress metrology | Bond yield, interface resistance/loss, thermal cycling and contamination | Mutually incompatible growth temperatures and chemistries |
| Energy harvester | Calibrated mechanical/thermal/optical excitation, rectifier, storage and power-management test | Power density under a declared source, impedance, lifetime and end-to-end duty cycle | Intermittency and harvested power below system leakage/peripheral demand |
G24 staged proof program
G24-A · SeparateBenchmark ionic, spin, optical and harvesting devices independently
G24-B · PairDemonstrate one useful transduction link at a time with full energy accounting
G24-C · TileBond small arrays and compare a defined temporal-learning or in-sensor task
G24-D · IntegrateAttempt monolithic processing only if heterogeneous integration wins measurably
Go/no-go criterionNEURO-SYNAPSE-OMNI advances only if the complete spin/opto/ionic path reduces measured task energy–delay or enables a function unavailable to an I5/I6 electrical baseline after lasers, magnets, converters, control and harvesting electronics are included.
13B · Quantum Processor Connectivity and Compatible Generations
Architecture boundaryNEURO-SYNAPSE-OMNI is not a quantum processor and does not replace qubits, quantum gates, error correction, microwave control, lasers, detectors, or the classical host. Its credible role is a separately qualified classical memory, temporal preprocessor, calibration engine, or adaptive controller connected to a quantum processing unit (QPU). Direct placement at the millikelvin stage is not assumed.
A quantum computer remains a hybrid system: a classical host schedules circuits, control electronics generate microwave, electrical, or optical pulses, the QPU evolves and is measured, and classical processors decode results and update calibration. Compatible OMNI generations would operate in this classical loop, reducing selected data movement or retaining adaptive state only if their heat, latency, noise, drift, and wiring costs beat CMOS or room-temperature alternatives.
Potential advantages in the classical quantum-control loop
| Potential advantage | Candidate generations | Preferred thermal stage | Quantum-control use | Required system proof | Reject condition |
|---|---|---|---|---|---|
| Persistent calibration near the controller | G1 first; G14/G16 conditional | 40–80 K or 4 K after qualification | Retain bias points, pulse envelopes, resonator maps or correction coefficients across controller cycles. | Lower reload traffic or calibration time at equal fidelity, including write energy and refresh. | Drift, write heat or finite endurance creates more recalibration than SRAM/flash. |
| Readout prefiltering and compression | G4/G12/G19/G21 | 40–80 K preferred; 300 K baseline | Extract events or temporal features before forwarding full readout records to the host. | Fewer transmitted bits and lower closed-loop latency without lost syndrome or state information. | ADC, array and link power exceed the cable or room-temperature processing saving. |
| Local drift and anomaly prediction | G19/G21; G1 digital-emulation control | 40–80 K or 300 K | Track fast disturbances and slower operating-point drift for scheduled recalibration. | Lower prediction error, fewer interrupted experiments and improved uptime versus a matched digital model. | No QPU-level gain after training, temperature variation and false interventions are counted. |
| Reduced feedback-loop traffic | G1/G16/G19 | 4 K only after 40–80 K success | Cache recent state and bounded control parameters beside cryo-CMOS while the FPGA or CPU remains authoritative. | Lower end-to-end latency, jitter, line activity or total cryostat heat at equal control accuracy. | Converters, static leakage, thermalized wiring or redundancy erase the device-level advantage. |
| Adaptive experiment memory | G1/G16/G19 | 300 K or 40–80 K | Store pulse history, detector context and frequently reused experiment parameters close to the scheduler. | Higher experiment throughput or lower host-memory traffic with deterministic recovery and audit logs. | Analog uncertainty compromises reproducibility, traceability or safety interlocks. |
| Modality-specific transduction | G9 optical; G23 spin; G24 combined | Stage separated and heterogeneous | Explore electrical memory beside photonic, spin or optical control hardware without placing unqualified media near qubits. | Measured information transfer, loss, noise, cross-talk and task energy beat a conventional transducer chain. | Fidelity or coherence degrades, or the transducer has no net advantage after sources and detectors. |
Quantum advantage terminology: these are potential advantages for the classical support electronics of a QPU. They are not evidence of quantum speed-up, additional qubit coherence, improved gate fidelity or fault tolerance. Such claims require an end-to-end QPU experiment against a matched controller baseline.
Recommended thermal partition
300 K · HostCompilation, scheduling, training, long-term logs, fleet calibration, and G1–G24 development software
40–80 K · Preprocessor optionG1 reference or qualified G12/G14–G21 memory for filtering, buffering, and calibration-state retention
4 K · Cryogenic controller optionLow-duty G1/G16/G19 test tile with local readout, strict heat and noise budget, and conventional cryo-CMOS fallback
10–100 mK · QPUQubits, resonators, couplers, first-stage amplification, and only components proven not to disturb coherence
The preferred first connection is therefore heterogeneous and stage-separated: the QPU stays at its validated base temperature, while an OMNI test die sits at a warmer cryostat stage or outside the cryostat. Thermalized electrical lines, optical fibre, or a qualified RF link carry only the signals required by the declared control task.
Selected G1–G24 compatibility with quantum-control functions
| Generation | Potential quantum-system role | Preferred location | Compatibility level | Principal blocker | Proof gate |
|---|---|---|---|---|---|
| G1 · Oxide reference | Calibration-state memory, lookup tables, pulse-history logging, and cryogenic electronics baseline | 300 K, 40–80 K, then 4 K test | Best near-term control | Write heat, variability, and cryogenic model accuracy | Retention, endurance, switching energy, and noise measured at each declared stage without measurable qubit degradation |
| G10 · Ho₂S₃ host | Materials-only cryogenic transport control; no assigned operational QPU role yet | Laboratory probe station, not QPU package | Characterization only | No demonstrated Ho₂S₃ memristor or low-temperature switching law | Reproducible phase, transport, switching, and thermal-cycle data before any integration study |
| G14 · Sc series | Test whether composition can reduce calibration-memory variability | 300 K or 40–80 K | Conditional support | Sc effect, linearity, and filament bias remain unmeasured | Statistically superior distributions versus G10/G1 controls at equal energy and temperature |
| G4 · Ag hybrid | Short-timescale event filter or pulse-history state for calibration loops | 40–80 K; 4 K only after kinetics proof | Conditional temporal role | Ag filament stochasticity, contamination, retention, and low-temperature dissolution | Useful, repeatable decay distribution and bounded write heat under cryogenic pulse protocols |
| G12 · Te-buffered Ag | Potentially smoother adaptive calibration update than G4 | 40–80 K | Conditional analog role | Ag–Te phase activity and release law may change at low temperature | Wider usable update window than G4 with measured phase stability and no added QPU noise |
| G15 · Fluorosulfide | Environmentally stabilized memory candidate for repeated cryostat cycling | 40–80 K or 4 K test coupon | Qualification enabler | Fluorination does not imply cryogenic mobility, radiation hardness, or stability | Improved thermal-cycle and storage survival without loss of switching function |
| G16 · Ca forming-control | Candidate low-voltage local state store that could reduce initialization energy and high-voltage wiring | 4 K controller stage if proven; otherwise 40–80 K | Strong future candidate | Forming-free yield, leakage, and charge-compensation window are unproven | First-cycle operation and full cold-stage energy beat G15 and cryo-CMOS memory alternatives |
| G21 · Ag/Li dual-timescale | Adaptive calibration, drift prediction, anomaly filtering, or local decoder state with fast and retained timescales | 40–80 K preferred; 4 K exploratory | Most relevant adaptive candidate | Li transport at 4 K, Ag/Li interference, write heat, and state attribution | Closed-loop QPU task improves calibration time or fidelity after all read/write and communication costs |
| G24 · Spin–opto–ionic | Optional optical or spin transducer between a QPU/control modality and a qualified G19/G21 memory tile | Separate bonded module at its own optimal temperature | Frontier interface option | Conversion loss, magnetic fields, optical heating, process incompatibility, and compound yield | One complete source-to-memory-to-controller link enables a unique function or beats the electrical interface in energy–delay and fidelity |
Connectivity by quantum-processor modality
| QPU platform | Native control/readout | Most credible OMNI connection | Compatible generations | Do not claim without proof |
|---|---|---|---|---|
| Superconducting qubits | Microwave pulses and dispersive RF readout at millikelvin temperatures | Warm-stage calibration memory, syndrome/readout prefilter, drift tracker, or pulse-parameter cache behind cryo-CMOS/RF converters | G1 first; G15/G16/G19 conditional | Direct mK placement, coherence improvement, or lower total cryostat power from device energy alone |
| Semiconductor spin qubits | DC/RF gate voltages, microwave control, charge or spin readout | Local bias-history memory and adaptive tuning engine; G23 spin conversion only as a separately measured option | G1, G16, G19; G23 exploratory | Useful spin coupling from Ho or Co chemistry without measured exchange, damping, field, and noise |
| Trapped ions / neutral atoms | Laser frequency, phase, amplitude, imaging, and real-time classical feedback | Room-temperature or intermediate-stage event/image preprocessing, laser-calibration memory, and adaptive scheduling | G1, G4, G12–G21; G9 optical option | Removing the laser/control stack or obtaining free optical communication |
| Photonic quantum processor | Optical sources, interferometers, phase shifters, switches, and photon detectors | Electrical memory beside silicon photonics; optional G9 optical modulation after loss and noise qualification | G1, G9, G19, G21; G24 system option | Single-photon compatibility, quantum-state preservation, or net advantage from Er/Bi₂Te₃ composition alone |
Closed-loop connection and acceptance metrics
1 · Measure QPUDigitize readout with timestamp, confidence, temperature, and operating point
2 · Update classical stateStore drift, calibration, syndrome, or temporal features in a qualified G1/G16/G19 device
3 · DecideCMOS or FPGA computes the bounded control action; the memory does not replace the decoder
4 · ReprogramDAC/RF/laser electronics apply the next pulse while enforcing amplitude, latency, and heat limits
5 · CompareBenchmark against DRAM/SRAM/flash plus cryo-CMOS at equal fidelity, duty cycle, and wiring
| Acceptance metric | Required measurement | Reject condition |
|---|---|---|
| Cold-stage heat | Dynamic write/read energy, static leakage, cable conduction, converter power, and duty cycle at every temperature plate | Added heat reduces cooling margin or forces a lower QPU duty cycle |
| Qubit disturbance | T₁, T₂, gate/readout fidelity, spectral noise, magnetic/optical cross-talk, and quasiparticle or charge effects with the controller idle and active | Statistically significant degradation beyond the allocated error budget |
| Control latency | End-to-end measurement-to-actuation latency, jitter, throughput, and queueing under the real feedback workload | No improvement over the conventional controller or deadline misses increase |
| Adaptive value | Calibration time, drift prediction error, decoder performance, uptime, and logical/physical error rate versus a matched digital baseline | Device-level adaptation does not improve a QPU-level metric after retraining and peripheral costs |
| Cryogenic reliability | Cooldown cycles, retention, endurance, write disturb, state drift, package stress, and failure distributions | State loss, delamination, contamination, or recalibration burden exceeds the baseline |
Recommended development order: connect a room-temperature G1 emulator to a live QPU control API; move a conventional G1 test die to 40–80 K and then 4 K; evaluate G16 only after forming-free statistics exist; evaluate G19/G21 at 40–80 K before any 4 K claim; and fund G23/G24 transduction only when a named QPU modality and metric justify it.
Canadian sovereignty boundary
Canadian and Quebec geology or recycling may offer Bi, Te, Ho, Er, Sc, Li, Ag and other feedstock pathways, but that is not “total sovereignty.” Separated Er/Ho, semiconductor-grade Bi₂Te₃ sources, epitaxy targets, lasers, magnetic metrology, specialty gases, lithography, packaging and foundry capacity may remain internationally sourced. A sovereign claim requires qualified suppliers, conversion routes, equipment support, contracts, capacity and lifecycle evidence for every critical stage.
15Quebec / Canada Supply-Chain Strategy
Canada offers credible upstream sources or development projects for the principal elements. A fully sovereign device supply chain still requires qualification of purity, refining, precursor synthesis, electrodes, deposition targets, packaging, production capacity, and commercial availability.
Quebec and Canada provide strategic upstream options, including scandium pathways at Sorel-Tracy and Nunavik, lithium projects in Baie-James, and silver/tellurium production. These resources do not yet constitute a fully domestic device-grade chain; refining, conversion, electronic-grade purity, qualified suppliers, processing capacity, and contracts remain to be demonstrated.
Status vocabulary“Operating” means current extraction, processing, manufacturing, or an established service; “project/resource” means development or geological potential, not available supply; “R&D capability” means a technical organization or pilot asset, not a commercial source. None of these labels implies semiconductor-grade purity or an offtake agreement.
Highest supply exposure
ITO, Au and Nb need second-source, recycling and substitution plans. ZnO, Al2O3, SiO2 and TiN reduce raw-material risk but not qualification cost.
Quebec reservoir scale
Cu–Te has the strongest bulk industrial narrative. Ag–Te and (Ag,Li)–Te remain credible specialty-material routes, with lithium adding strategic value but substantially more process complexity.
| Element | Role in the chip | Canadian source |
|---|---|---|
| Scandium (Sc) | Candidate strain and defect-energy modifier | Sorel-Tracy, QC titanium-process residues; Crater Lake primary-resource project in Nunavik; bauxite residue is a separate recovery R&D pathway |
| Copper (Cu) | Alternative ECM reservoir and BEOL-familiar conductor | Quebec mining, smelting, and refining ecosystem; device-grade purity requires qualification |
| Gold (Au) | Nominally inert electrode for VCM control cells | Quebec gold-mining ecosystem; high cost favours laboratory controls over active reservoirs |
| Lithium (Li) | Candidate cation for a retained insertion response | Baie-James / Eeyou Istchee, QC (Whabouchi-class spodumene) |
| Silver (Ag) | Fast STP cation source | Abitibi, QC polymetallic mines |
| Tellurium (Te) | Ion-kinetics buffer | Byproduct of Abitibi / Rouyn-Noranda copper refining |
| Holmium (Ho) | Host matrix cation | Canadian rare-earth projects + magnet-recycling streams |
| Calcium (Ca) | Candidate defect-compensation dopant | Abundant domestic minerals; electronic-grade precursor conversion remains necessary |
| Sulfur (S) | Mobile anion sublattice | Petrochemical byproduct, QC/AB |
| Fluorine (F) | Candidate chemical passivation | Domestic fluorochemical capability; radiation tolerance requires device testing |
| Erbium (Er) | G24 near-infrared optical-emitter candidate | Canadian mixed rare-earth projects and separation/recycling R&D; separated electronic-grade Er remains to be qualified |
| Bismuth (Bi) | G23 Bi₂Te₃ topological-interface constituent | Potential Canadian polymetallic by-product and recycling pathways; semiconductor-grade Bi₂Te₃ source and stoichiometry remain import/qualification risks |
Global resource production: five leading countries
Estimated 2025 production from the USGS Mineral Commodity Summaries 2026. Quantities use the reporting basis and unit shown; they are not interchangeable with electronic-grade material, qualified precursor, target, wafer, or foundry capacity.
Reading boundaryHo and Er are not reported separately, so total rare-earth mine production is only an upstream proxy. Sc country volumes are not published on a comparable basis. Ca is represented by lime, F by fluorspar, Hf by zirconium mineral concentrates, and Ti by ilmenite. Tellurium is mainly refinery byproduct output; the Sweden figure is concentrate. “W” means withheld by USGS.
| Resource / OMNI use | 2025 basis and unit | 1st producer | 2nd producer | 3rd producer | 4th producer | 5th producer | World total | Interpretation limit |
|---|---|---|---|---|---|---|---|---|
| Silver (Ag) Fast STP reservoir | Mine, t Ag content | Mexico · 6,300 | Peru · 3,600 | China · 3,400 | Bolivia · 1,500 | Chile · 1,400 | 26,000 t | Mostly a byproduct; mine output does not certify 4N–6N electrode stock. |
| Lithium (Li) Slow LTP ion | Mine, t Li content | Australia · 92,000 | China · 62,000 | Chile · 56,000 | Zimbabwe · 28,000 | Argentina · 23,000 | 290,000 t, excluding withheld U.S. output | Brine and hard-rock products differ; battery grade is not automatically device grade. |
| Tellurium (Te) Kinetics buffer / Bi₂Te₃ | Refinery, t Te content | China · 800 | Russia · 67 | Japan · 61 | Sweden · 48 (concentrate) | Canada · 28 | ~1,000 t, excluding U.S. W and unquantified producers | Byproduct recovery tracks electrolytic copper refining; several producing countries are unquantified. |
| Holmium + erbium proxy (Ho/Er) Host / G24 optical dopant | Rare-earth mine, t REO equivalent | China · 270,000 | United States · 51,000 | Australia · 29,000 | Burma · 22,000 | Thailand · 4,800 | 390,000 t REO | Mixed-REE tonnage does not disclose Ho/Er content, separation yield, purity, or export availability. |
| Scandium (Sc) Defect / strain modifier | Byproduct Sc₂O₃, t | China · leading producer; quantity NA | Philippines → Japan · quantity NA | Other ranks · NA | Not reported | Not reported | ~80 t global output; >90 t/y capacity | No defensible public top-five quantity table; Canada reported a 9 t/y capacity expansion, not equivalent production. |
| Calcium proxy (Ca) Compensation dopant | Lime, thousand t product | China · 310,000 | India · 17,000 | United States · 15,000 | Russia · 12,000 | Brazil · 8,200 | 420,000 kt | Bulk quicklime/hydrated lime is a scale proxy, not high-purity Ca precursor supply. |
| Sulfur (S) Anion sublattice | All forms, thousand t S content | China · 19,000 | United States · 8,100 | Russia · 7,500 | Saudi Arabia · 7,200 | United Arab Emirates · 6,300 | 84,000 kt | Mostly recovered from fuels or smelting; electronic-grade sulfide chemistry is downstream. |
| Fluorine proxy (F) Passivation candidate | Fluorspar mine, thousand t product | China · 6,000 | Mexico · 1,500 | Mongolia · 1,500 | South Africa · 410 | Vietnam · 160 | 10,000 kt | CaF₂ tonnage does not measure semiconductor-grade HF or fluorochemical capacity. |
| Bismuth (Bi) G23 Bi₂Te₃ interface | Refinery, t Bi | China · 14,000 | Republic of Korea · 1,000 | Japan · 500 | Laos · 500 | Bolivia / Bulgaria · 50 each | 16,000 t | Refinery byproduct output; the fifth position is tied and does not indicate Bi₂Te₃ crystal quality. |
| Copper (Cu) Alternative ECM / interconnect | Mine, thousand t Cu content | Chile · 5,300 | Congo (Kinshasa) · 3,200 | Peru · 2,700 | China · 1,800 | Russia · 1,300 | 23,000 kt | Mine ranking differs from refinery ranking and foundry-approved electronic copper. |
| Gold (Au) Inert control electrode | Mine, t Au content | China · 380 | Russia · 310 | Australia · 280 | Canada · 200 | United States · 160 | 3,300 t | Mine output is not deposition-pellet purity, traceability, or available fabrication capacity. |
| Platinum-group metals (PGM) Electrodes / catalysts | Mine, kg Pd + Pt content | South Africa · 190,000 | Russia · 104,000 | Zimbabwe · 33,000 | Canada · 21,000 | United States · 8,000 | 360,000 kg Pd + Pt | Calculated sum of USGS palladium and platinum rows; other PGMs and recycling are excluded. |
| Hafnium proxy (Hf/Zr) High-k / specialty electrode chain | Zirconium mineral concentrate, thousand t gross | Australia · 400 | South Africa · 270 | Mozambique · 160 | China · 100 | United States · 100 | 1,200 kt | Hf is recovered during Zr purification; primary Hf country production is not quantitatively reported. |
| Titanium feedstock (Ti) Barriers / process equipment | Ilmenite mine, thousand t concentrate | China · 3,200 | Mozambique · 1,900 | South Africa · 1,300 | Australia · 780 | Norway · 390 | 9,400 kt ilmenite | Concentrate is not Ti metal, TiN barrier material, or semiconductor sputter-target capacity. |
| Tungsten (W) Contacts / tooling | Mine, t W content | China · 67,000 | Vietnam · 3,000 | Kazakhstan · 2,400 | Russia · 2,000 | North Korea · 2,000 | 85,000 t | Russia and North Korea tie; concentrate output is upstream of electronic-grade CVD precursors. |
| Silicon (Si) CMOS substrate / unconventional resource | Silicon metal, thousand t Si content | China · 4,000 | Brazil · 180 | Norway · 130 | France · 68 | Australia · 47 | 4,600 kt, excluding U.S. W | Metallurgical silicon is not polysilicon, electronic-grade crystal, wafer, or fab capacity. |
Top-five producer concentrationsupply-risk context
Approximate share of reported world output represented by the five listed producers. Different commodities use different units and proxies; bars must not be compared as physical tonnage.
Province and territory contribution map
| Province / territory | Relevant upstream materials | Processing, manufacturing, or research contribution | Status and role for NEURO-SYNAPSE-OMNI | Qualification gap |
|---|---|---|---|---|
| Quebec | Sc from titanium-process residues; Li, Au, Ag, Cu and rare-earth projects/resources; sulfur and industrial minerals | Sorel-Tracy scandium recovery; mining/metallurgical corridor; Bromont microelectronics, advanced packaging and research ecosystem | Core hub: strongest combination of candidate feedstocks, circular Sc, device R&D and packaging | Ho and Sc precursor conversion, sputter-target purity, qualified sulfide deposition, contracts and production scale |
| Ontario | Operating Au and base/precious-metal production; Cu, Ni, Co and platinum-group-metal streams | Sudbury metallurgical cluster; Toronto–Waterloo–Ottawa university, photonics, semiconductor-design and nanofabrication ecosystem | Operating + R&D: electrode metals, analytical services, circuit design and test | Traceable Ag/Au/Cu lots and conversion to contamination-controlled electronic materials |
| British Columbia | Operating Cu and Au production; Ag and other by-products; molybdenum resources | Smelting/refining and port access; Vancouver compound-semiconductor, quantum and clean-technology ecosystem | Operating + logistics: copper-rich western source and Pacific import/export route | Separate bulk concentrate/refined metal from device-grade electrode or precursor supply |
| Alberta | Large elemental-sulfur output associated with oil and gas processing; limestone/calcium-bearing industrial minerals | Petrochemical purification, gas handling, process engineering and carbon/energy infrastructure | Operating: strongest domestic bulk-sulfur pathway and hazardous-gas/process expertise | Ultra-high-purity sulfur or sulfide precursor specification, packaging, transport and contamination control |
| Saskatchewan | Uranium, potash and critical-mineral resources; rare-earth-bearing feedstock opportunities | Saskatchewan Research Council rare-earth processing and metallurgical pilot capabilities | Pilot/R&D: separation, hydrometallurgy and rare-earth processing knowledge relevant to Ho purification | Demonstrated Ho-specific separation, purity, capacity, economics and commercial availability |
| Manitoba | Ni–Cu–Co–Zn mining history and lithium/cesium-bearing pegmatite resources/projects | Central transport position and mining/metallurgical workforce | Operating + project mix: potential Li and base-metal diversification | Verify current mine/project status, refining destination, product specification and dependable volume |
| Newfoundland and Labrador | Operating Ni–Cu–Co production; iron ore; rare-earth and fluorite prospects/projects | Atlantic ports, hydrometallurgical expertise and access to Labrador mineral districts | Operating + project mix: base-metal stream and possible future F/REE diversification | No assumption of operating Ho or fluorine supply; project maturity and product pathway require confirmation |
| New Brunswick | Base-metal and polymetallic geology; industrial minerals | Atlantic logistics, fabrication and university materials research | R&D/logistics: alternate eastern testing and transport capability | Do not count historical mines or closed processing assets as current supply |
| Nova Scotia | Gypsum, limestone and other industrial-mineral production | Halifax port, ocean logistics, universities and sensor/microelectronics research | Operating + R&D: calcium-bearing industrial input and Atlantic system-testing links | Electronic-grade Ca compound conversion and environmental footprint |
| Yukon | Au, Ag, Cu, Zn and critical-mineral resources/projects | Exploration expertise and western/northern logistics | Project/resource: long-term polymetallic diversification | Permitting, infrastructure, Indigenous partnership, economics, operating status and refining route |
| Northwest Territories | Rare-earth and polymetallic resources/projects | Northern mining logistics and experience with high-value mineral concentrates | Project/resource: possible future rare-earth feedstock diversification | Operating continuity, mixed-REE separation into Ho, transport, cost and community agreements |
| Nunavut | Operating Au plus base-metal and critical-mineral exploration potential | Arctic logistics and mining operations | Operating + exploration: precious-metal diversification, not a complete materials chain | Infrastructure, seasonal logistics, refining destination and electronic-grade traceability |
| Prince Edward Island | No major critical-mineral mine, smelter, refinery or advanced project identified on the 2026 federal map | Potential downstream services, biosensing and research participation | Downstream only: no upstream claim | Participation would be through R&D, applications or services rather than mineral extraction |
Element-by-element Canadian diversification
| Needed input | Primary Canadian pathway | Secondary diversification | Procurement specification | Residual import exposure |
|---|---|---|---|---|
| Sc precursor | Quebec circular Sc₂O₃ from Sorel-Tracy | Crater Lake, QC project; future residue recovery research | Purity, U/Th/Fe/Ti/Na limits, lot consistency, particle size, conversion yield | Sulfide-compatible Sc precursor and deposition target may still require foreign processing |
| Ho precursor | Canadian mixed-rare-earth projects and recycling research | Saskatchewan separation expertise; northern REE resources/projects | Ho assay, neighbouring lanthanides, oxygen/carbon/halogen limits, isotopic/radiological certificate | Largest likely gap: separated commercial Ho and device-grade Ho compound availability |
| Li precursor | Quebec and Manitoba hard-rock pathways/projects | Ontario hard-rock projects and western/northern exploration | Battery/electronic grade is not interchangeable; specify Na, K, Mg, Ca, Fe, water and anion content | Conversion chemicals and Li-containing sputter/evaporation sources may be imported |
| Ag / Au electrodes | Quebec and Ontario precious-metal production | BC, Nunavut and Yukon production/resources | 4N–6N target as process requires; grain, gas, alkali and transition-metal impurities; chain of custody | High-purity targets and specialty evaporation pellets may rely on global fabricators |
| Cu electrode | BC, Ontario and Quebec mining/metallurgical streams | Manitoba and Newfoundland and Labrador base-metal streams | Electronic grade, oxygen content, target density, certified trace metals | Device-compatible target manufacturing and foundry-approved barriers |
| Te precursor | By-product recovery associated with Canadian copper metallurgy where commercially recovered | Recycling of photovoltaic, thermoelectric and metallurgical residues | Recovery location, purity, Se/Bi/Pb/Cu limits and stable by-product volume | Tellurium is a small by-product market; domestic availability must be contracted, not assumed |
| Sulfur / sulfide chemistry | Alberta elemental sulfur; Quebec/Canadian petrochemical sulfur | Industrial sulfur streams elsewhere in western Canada | Electronic-grade sulfur or certified precursor; water, oxygen, carbon and metal limits | Specialty H₂S/organosulfur gases and semiconductor packaging may be sourced globally |
| F precursor | Canadian chemical supply and potential fluorite project pathways | Newfoundland and Labrador and other fluorite prospects/projects | Exact precursor chemistry, water/oxygen/metal limits, cylinder and abatement compatibility | High-purity semiconductor fluorochemicals remain a probable import dependency |
| Ca precursor | Widespread Canadian limestone and industrial-mineral production | Quebec, Ontario and Atlantic industrial-mineral processors | Electronic-grade compound rather than bulk mineral; alkali, Mg, Fe and moisture limits | High-purity dopant source preparation may be external despite abundant geology |
Downstream Canadian semiconductor chain
1 · ResourceQC/ON/BC/MB/NL mines and projects; AB sulfur; northern REE potential
2 · Separate/refineQC scandium and metallurgy; ON/BC metals; SK rare-earth pilot capability
3 · Electronic materialPurify, synthesize sulfides/fluorides, press targets, certify every lot
4 · DeviceCanadian university/shared fabs and Quebec/Ontario microelectronics ecosystem
5 · Package/testBromont and national packaging, reliability, photonics, sensor and system partners
The strategic bottleneck is not total tonnes in the ground. It is the middle of the chain: separation of individual rare earths, conversion to oxygen- and moisture-controlled precursors, fabrication of dense deposition targets, semiconductor contamination certification, and repeatable small-volume delivery. Procurement should therefore maintain a source–processor–converter–target maker–fab traceability record for every material lot.
Supplier qualification scorecard
| Gate | Required evidence | Reject or hold condition |
|---|---|---|
| Commercial status | Operating asset, product catalogue, sample availability, lead time and capacity | Resource estimate or press release presented as saleable product |
| Chemistry | Certificate of analysis plus independent ICP-MS/GDMS, oxygen/carbon/sulfur and moisture tests | Unspecified trace impurities or analytical limits above device requirements |
| Lot consistency | At least three lots with statistical comparison and retained witness samples | Performance depends on one exceptional lot |
| Conversion | Mass balance from feedstock to precursor/target; yield and secondary-waste characterization | Canadian ore exported and re-imported without traceable conversion or impurity history |
| ESG and partnership | Permits, lifecycle boundaries, Indigenous consultation/agreements where applicable, worker and waste controls | “Ethical/local” claim without auditable project-specific evidence |
| Resilience | Dual source, minimum stock, recycling route, substitution plan and geopolitical/logistics assessment | Single unqualified source for Ho, Sc, Te or specialty fluorochemical |
Three Quebec scandium pathways
| Pathway | 2026 status used in this dossier | Strategic value | Qualification needed for Ho₂S₃:Sc |
|---|---|---|---|
| Sorel-Tracy circular production | Rio Tinto Fer et Titane recovers high-purity scandium oxide from titanium-process residues; this is distinct from Saguenay bauxite residue. | Existing Quebec circular-economy route and reduced dependence on a single foreign supply region | Batch availability, impurity certificate, conversion of Sc₂O₃ into a sulfide-compatible precursor, cost, and volume |
| Crater Lake primary resource | Scandium Canada development project in Nunavik, not treated here as current device-grade commercial production | Potential long-term primary source and North American resource diversification | Project schedule, refining route, product specification, offtake, logistics, and lifecycle assessment |
| Vaudreuil bauxite residue | Potential future recovery feedstock at the Jonquière alumina refinery; no device-grade scandium stream is assumed | Could couple residue remediation with critical-mineral recovery if concentration and process economics are favourable | Representative assays, mineralogy, extraction yield, reagent and energy balance, impurity removal, waste fate, and Sc₂O₃ purity |
Vaudreuil red-mud opportunity: figures to verify
Source boundaryThe project brief supplied figures of approximately 1 Mt/y of bauxite residue, roughly 40 Mt historically accumulated, more than C$250 million associated with the Vaudreuil 2022 transition, and filtered residue above 70% solids. These values are planning inputs only until checked against dated Rio Tinto, regulator, or government primary documents; they do not establish recoverable scandium tonnage.
Bauxite residue can contain scandium and rare-earth traces, but total residue mass is not an ore reserve. The relevant quantity is recoverable scandium after representative sampling, mineralogical characterization, leaching, separation, purification, and residue-stability testing. A defensible circular-economy claim therefore has four gates:
1 · AssaySc concentration, variability, mineral hosts, and contaminants
2 · RecoverYield, selectivity, reagents, water, energy, and secondary residues
3 · PurifyElectronic-material impurity limits and precursor conversion
4 · QualifyHo₂S₃:Sc phase purity, electrical statistics, cost, and lifecycle impact
The credible industrial pitch is conditional: investigate whether Quebec residues can become a qualified scandium precursor while reducing environmental liability. “100% local,” guaranteed remediation, and subsidy eligibility require traceable contracts, mass balances, lifecycle data, and program-specific review.
16Device Design & Experimental Plan
The minimum test vehicle is a (Ag,Li)-Te / (Ho,Sc,Ca)₂(S,F)₃ / inert-electrode cell. A platinum bottom electrode isolates injection from the reservoir; a 1T1R selector transistor provides current compliance and sneak-path protection in arrays.
Coupled mathematical model
A useful first model couples ionic drift–diffusion, electrostatics, interfacial charge transfer, electronic conduction, and heat. It should be calibrated separately for Ag⁺, Li⁺, and effective sulfur-defect populations rather than fitting one undifferentiated “memristor state.”
| Model component | Equation | Unknowns to measure or fit | Experimental link |
|---|---|---|---|
| Nernst–Planck flux | \(J_i=-D_i\nabla c_i-z_i u_i F c_i\nabla\phi\) | Di(T,c), molar mechanical mobility ui, effective charge zi, concentration ci | Temperature-dependent transients, isotope/SIMS profiles, time-of-flight estimates |
| Species continuity | ∂ci/∂t = −∇·Ji + Ri | Generation, trapping, recombination, insertion, and redox rate Ri | Pulse/recovery kinetics and post-bias depth profiles |
| Poisson electrostatics | ∇·(ε∇φ) = −ρ, ρ = FΣzici + ρtrap | Permittivity ε, trap charge, boundary potentials | Impedance spectroscopy, capacitance, thickness dependence |
| Interfacial redox | \(j=j_0\!\left[\exp\!\left(\frac{\alpha F\eta}{RT}\right)-\exp\!\left(-\frac{(1-\alpha)F\eta}{RT}\right)\right]\) | Exchange current j0, transfer coefficient α, overpotential η | Polarity and electrode series; scan-rate and temperature dependence |
| Activated transport | D(T) = D0 exp(−Em/kBT) | Prefactor D0 and migration barrier Em | Arrhenius plot only over a regime with unchanged mechanism |
| Electrothermal coupling | ρmCp∂T/∂t = ∇·(k∇T) + J·E | Thermal conductivity k, heat capacity Cp, interfaces and pulse power | Pulse thermometry, resistance thermometry, finite-element thermal model |
| Electrical readout | I = ∫Aσ(c,T,E)E·dA; Epulse = ∫V(t)I(t)dt | Conductivity law σ and active area A | High-bandwidth simultaneous voltage/current waveform capture |
Dilute-limit check: with the flux convention above, the molar mechanical mobility is ui = Di/(RT); the ionic charge appears once in ziF. Equivalently, one may define the electrical mobility μi = ziFDi/(RT) and write the drift term as −μici∇φ, without an additional ziF factor. Either dilute-limit relation may fail in a concentrated, correlated solid electrolyte. Butler–Volmer kinetics may likewise need Marcus, nucleation, or field-assisted corrections. Model selection should be based on residuals and prediction of held-out pulse sequences, not fit quality alone.
First-order design calculations
| Design quantity | Calculation | Example | Use |
|---|---|---|---|
| Electric field | E = V/d | 0.2 V across 10 nm gives 20 MV/m | Compare thicknesses by field, not voltage alone; include voltage lost at interfaces and series resistance |
| Compliance resistance | Rseries ≥ V/Icomp | 0.2 V / 10 µA = 20 kΩ | Initial passive protection; an active transistor or SMU compliance is still preferred |
| Current density | J = I/A | 10 µA through 100 × 100 nm² gives 10⁵ A/cm² | Geometric average over the full junction, not a recommended operating density. It is already high for a memory cell; a narrower metallic filament can experience still larger local density and severe Joule heating. |
| Areal density | N = 1/p² | 100 nm square pitch gives 10¹⁰ cells/cm² | Geometric upper bound before selectors, vias, redundancy, and routing |
| Cell capacitance | C ≈ ε0εrA/d | Must use measured εr and actual overlap area | Separates displacement current from ionic/electronic switching current |
| Energy budget | Q = ∫I dt; E = ∫VI dt | At constant 0.2 V, 0.5 pJ permits Q ≤ 2.5 pC; at 10 µA this corresponds to at most 250 ns | Defines integrated charge over the pulse, not current alone; subtract cable and instrument charging artefacts |
Test-chip and mask design
Begin with large structures that decouple material physics from nanofabrication yield, then shrink only after the mechanism is identifiable. A practical first mask set contains isolated MIM cells, van der Pauw/Hall structures, transmission-line contacts, Kelvin structures, capacitors, line/space monitors, and small crossbars.
| Vehicle | Suggested screening geometry | Purpose | Progression criterion |
|---|---|---|---|
| Blanket film coupon | 10–25 mm coupon; several composition witnesses | Phase, thickness, roughness, composition, optical and thermal stability | Uniform single/controlled phase and reproducible stoichiometry |
| Large MIM dot | 10–100 µm diameter; 5–50 nm active-film matrix | Fast screening with low lithographic risk | Area/thickness trends and electrode controls identify a plausible mechanism |
| Scaled crosspoint | 0.1–10 µm junctions | Test scaling, current density, variability, and parasitics | No catastrophic leakage increase; switching statistics remain separable |
| Small passive array | 4×4 to 32×32 | Sneak paths, line resistance, half-select disturbance | Read/program margin survives array bias scheme |
| Selector-integrated tile | 1T1R first; 1S1R after selector qualification | Compliance, addressing, endurance, and system energy | Array-level yield and energy include peripheral circuitry |
Control devices
- Ag-only controls: Ag / Ho₂S₃:Sc / Pt, pure Ag / (Ho,Sc,Ca)₂(S,F)₃, and (Ag,Li)-Te / undoped Ho₂S₃ cells to separate active-metal, host, dopant, and buffer contributions.
- Inert-electrode controls: Au / Ho₂S₃:Sc / Pt and Pt / matrix / Pt devices to characterize host VCM, traps, and interfaces without intentionally injected Ag or Cu.
- Reservoir comparison: Au control, Ag–Te, Cu–Te, AgCu–Te composition series, (Ag,Li)–Te, and Li-only insertion controls at matched geometry and pulse conditions.
- Composition series: multiple Ag:Li:Te and Ag:Cu:Te ratios, Sc concentrations, Ca concentrations, and layer thicknesses.
Materials characterization
- Structure & phase: XRD for lattice strain from Sc substitution; XPS for oxidation states and Ho–F bonding.
- Depth profiling: SIMS to track Ag, Li, and Te distributions before/after cycling and BEOL-relevant anneals (400 °C).
- Nanoscale imaging: TEM/EELS and in-situ or operando methods to test for conductive-path correlation with Sc-rich regions and for any Li-related composition front.
Fabrication method and process controls
1 · SubstrateSolvent/UV-ozone clean, dehydration, alignment marks, witness coupons
2 · Bottom metalPattern Pt/TiN control electrodes; measure sheet/contact resistance
3 · Active filmDeposit Ho₂S₃ and Sc series; control sulfur chemical potential and thickness
4 · Optional dopantsAdd F/Ca only after G2/G3 baselines; retain composition witnesses
5 · ReservoirPattern Au, Ag, Cu, Ag–Te, or (Ag,Li)–Te controls in dedicated modules
6 · EncapsulationApply chemically compatible barrier; compare capped and uncapped ageing
7 · Pattern/etchLift-off or qualified low-damage etch; verify sidewall residues and shorts
8 · TestWafer map, randomized pulse protocol, post-mortem chemistry and microscopy
Process traveler, inline metrology and release gates
| Module | Variables to lock | Inline witness / metrology | Likely failure | Corrective route | Release gate |
|---|---|---|---|---|---|
| Incoming materials | Lot, purity, water/oxygen/carbon/metals, particle size, target density and storage history. | Certificate cross-check, ICP-MS/GDMS where justified, moisture/oxygen assay and retained sample. | Trace impurity changes leakage, nucleation or phase without appearing in nominal composition. | Quarantine lot; tighten impurity limits; qualify a second source; correlate impurity fingerprints with electrical lots. | No deposition until identity, impurity limits, chain of custody and safe handling are accepted. |
| Substrate / bottom electrode | Surface termination, roughness, sheet resistance, adhesion, texture, clean delay and vacuum break. | Contact angle or surface proxy, AFM coupon, four-point probe, Kelvin/TLM structures and optical inspection. | Residue or roughness creates local-field hot spots and false filament localization. | Use a time-bounded clean-to-load sequence, smoother seed/barrier, sacrificial witness and contact-resistance gate. | Uniform resistance and roughness remain inside the preregistered baseline window. |
| Ho–Sc–S host | Source power/flux, sulfur activity, pressure, substrate temperature, thickness, rotation and post-anneal atmosphere. | Thickness map, XRR/profilometry, composition map, capped XRD/XPS witnesses and four-point leakage coupon. | Sulfur loss, mixed phase, pinholes, oxygen uptake or composition gradient dominates switching. | Increase sulfur chemical potential within equipment/EHS limits, lower thermal budget, use alternating/nanolaminate deposition, densify cap, or down-select an amorphous/oxysulfide host. | Three independent runs meet phase, composition, thickness, roughness and leakage distributions. |
| Sc / Ca / F incorporation | Dose, source calibration, sequence, site availability, plasma damage, precursor residue and depth profile. | RBS/ERDA or calibrated XPS/SIMS, XRD, witness capacitors, impurity monitors and bonding spectroscopy. | Segregation or secondary CaS/CaF₂/Sc-rich phase is mistaken for beneficial defect engineering. | Reduce dose, localize dopant at an interface, switch to digital-alloy pulses, lower energy, or remove the dopant if the causal metric does not survive controls. | Measured site/phase evidence plus electrical improvement versus the immediately simpler host. |
| Ag–Te / Ag–Li–Te reservoir | Atomic ratio, phase, thickness, grain size, oxidation exposure, source history and pattern overlap. | XRD/Raman, XPS, composition/thickness maps, sheet resistance and pre-bias SIMS witness. | Pure Ag-rich path produces abrupt shorts; Te-rich phase blocks switching; Li redistributes before test. | Use a composition gradient, nanolaminate, diffusion barrier, reduced reservoir thickness, colder processing, inert transfer, or separate Ag/Li devices. | Reservoir phase and depth profile reproduce, with no spontaneous cross-layer diffusion after the declared thermal budget. |
| Pattern / etch / lift-off | Resist profile, exposure, etch chemistry/energy, endpoint, sidewall angle, redeposition and solvent compatibility. | CD/overlay monitors, blanket etch-rate coupon, SEM/AFM, open/short combs and residue-sensitive XPS. | Sidewall redeposition or undercut shorts cells; plasma damage creates the apparent switching layer. | Prefer lift-off for early large cells, use hard masks/low-energy milling, add sidewall dielectric, clean with chemistry-qualified steps and compare unpatterned capacitors. | Open/short yield and leakage map pass before pulse-learning data are interpreted. |
| Encapsulation / bond | Barrier material, pinholes, stress, cure temperature, adhesion, water-vapor/oxygen transmission and edge seal. | Capped/uncapped witnesses, wafer bow, adhesion test, humidity soak, leak test and post-bond interface resistance. | Cap reacts with sulfide/F/Li, traps contamination, cracks, or adds stress-induced drift. | Insert chemically inert liner, reduce cure temperature, use multilayer moisture barrier, move G9 modules to transfer bonding, and retain edge-seal controls. | Packaged and uncapped controls separate intrinsic ageing from package benefit or damage. |
| Electrical sort | Probe force, cable correction, compliance, read bias, pulse charge, temperature, sequence and randomization. | Open/short standards, reference cells, current waveform capture, device-temperature proxy and automated audit log. | Instrument bandwidth, capacitive transient, Joule heating or read disturb is labeled as memory. | Subtract displacement current, measure actual device voltage/current, use polarity/energy/dummy-capacitor controls and enforce a read-disturb gate. | State separation survives correction, controls, repeated devices and a second run/operator. |
Fabrication tipDo not shrink the first mask set to maximize density. Large MIM cells, Kelvin contacts, Hall bars, capacitors, line/space monitors and capped witnesses reveal whether failure comes from chemistry, contacts, patterning or array routing before nanoscale yield obscures the cause.
Technology-blocker solution playbook
| Blocker | Fast discriminating check | Primary solution | Fallback / stop rule |
|---|---|---|---|
| No stable Ho₂S₃ film | Capped composition/phase map before electrical patterning. | Sulfur-rich low-temperature process, inert transfer and immediate barrier cap. | Use an amorphous sulfide, oxysulfide/bilayer or terminate the pure-host route after two bounded learning cycles. |
| Switching is contact artefact | Thickness and electrode-work-function series plus four-terminal/Kelvin structures. | Engineer a reproducible interface and model contact/bulk contributions separately. | Reframe as interface memory only if it remains repeatable and useful; otherwise stop. |
| Ag produces hard shorts | High-bandwidth current transient and post-mortem Ag map at equal delivered charge. | Charge termination, thinner/buffered reservoir, nucleation layer and hard selector compliance. | Use Cu or nanoclusters, or separate the volatile element from the retained synapse. |
| Li and Ag cannot be separated | Ag-only, Li-only, isotopic full-factorial depth/time controls. | Ion-selective barriers, sequential pulse windows and spatially separated reservoirs. | Adopt a paired fast/slow two-cell synapse if timescale distributions remain inseparable. |
| F suppresses switching | Low-F gradient at matched host phase and leakage. | Confine F to a passivating interface or replace bulk fluorination with encapsulation. | Return to G5 chemistry when resilience gain does not offset plasticity loss. |
| Ca compensation raises leakage | Constrained y/z/δ mixture with impedance and first-cycle yield. | Reduce/localize Ca and control vacancy population through process atmosphere rather than nominal formula alone. | Retain controlled forming at G6 if no forming-free window preserves retention. |
| Variability erases analog bits | Hierarchical C2C/D2D/run variance and adjacent-state d′. | Differential/reference cells, verify-write, pulse-charge control, redundancy and algorithm-aware calibration. | Use binary/event operation when effective analog precision does not beat G1. |
| BEOL contamination rejected | Blanket diffusion/outgassing monitor through the foundry thermal budget. | Dedicated module, qualified barriers, wafer-edge exclusion and contamination accounting. | Move novel chemistry to a bonded chiplet rather than forcing monolithic integration. |
| Peripheral energy dominates | Rail-resolved task energy including ADC/DAC, drivers, calibration, routing and idle power. | Lower converter resolution, exploit sparsity, local accumulation, event gating and duty cycling. | Stop scaling the custom material if no measured task energy–delay benefit survives system accounting. |
| G24 coupling adds loss, not function | One transduction link versus an electrical G21/G22 baseline with all source/detector costs. | Optimize and bond modules independently; retain only the channel with unique function or net benefit. | Remove Bi₂Te₃/Er/spin/harvesting modules that do not clear their own exit gate. |
Safety and contaminationSulfidation routes involving H₂S or other toxic sulfur precursors require an engineered gas cabinet, automatic detection, interlocks, exhaust and scrubber, written emergency procedures, and trained institutional operation. Ag, Li, Te, F, rare-earths, and sulfur processes should use approved dedicated or contamination-controlled tooling; this dossier is not a hazardous-gas operating recipe.
Machines and laboratory infrastructure
| Work package | Minimum viable equipment | Advanced / shared facility | Output |
|---|---|---|---|
| Powder/target preparation | Inert glovebox, analytical balance, sealed mixing/milling capability, vacuum/inert furnace | Hot press or spark-plasma sintering, ICP-MS/OES | Traceable precursors or sputter targets with impurity certificate |
| Thin-film deposition | RF/DC magnetron sputter or thermal/e-beam evaporation with substrate rotation and quartz monitor | Multi-source co-sputtering, PLD, ALD/CVD where suitable, in-situ RHEED/XPS | Thickness- and composition-controlled Ho–Sc–S, metals, and reservoir films |
| Lithography | Spin coater, hotplates, UV mask aligner, microscope, lift-off wet bench | Direct-write laser or electron-beam lithography; stepper for arrays | Large MIM cells through submicron crosspoints |
| Etch and clean | Approved wet process and solvent benches, oxygen plasma/UV ozone where compatible | RIE/ICP, ion milling, endpoint monitoring | Defined mesas/electrodes with controlled sidewalls and residues |
| Physical metrology | Profilometer, ellipsometer, four-point probe, optical microscope, AFM access | X-ray reflectometry, SEM, cross-sectional FIB | Thickness, roughness, uniformity, dimensions, sheet resistance |
| Structure/chemistry | XRD and XPS access | GI-XRD, Raman, SIMS, TEM/STEM-EDS/EELS, EPR, synchrotron methods | Phase, strain, oxidation state, dopant location, depth profiles and defect evidence |
| Electrical test | Shielded probe station, low-noise SMU, pulse generator, oscilloscope, LCR/impedance analyzer | Semiconductor parameter analyzer, pulse/measure unit, switching matrix, wafer prober | I–V, pulse energy, impedance, noise, endurance, device/wafer distributions |
| Environment/reliability | Hot chuck, controlled-humidity chamber, inert storage, temperature logging | Vacuum cryostat, thermal-vacuum chamber, radiation facility, high-temperature probe station | Retention, atmosphere sensitivity, thermal cycling, 4 K and radiation qualification |
| Simulation/data | Version-controlled analysis workstation with uncertainty/statistics software | DFT/NEB HPC cluster and multiphysics finite-element solver | Defect energetics, field/thermal maps, DOE analysis, reproducible raw-data pipeline |
Design of experiments and statistics
A full Cartesian sweep becomes unmanageable quickly. Use staged DOE: first screen main effects, then optimize only factors that survive physical and statistical gates. Randomize measurement order, block by wafer/deposition run, blind device identifiers during analysis where practical, and preserve every failed or shorted device in the denominator.
| Stage | Factors | Suggested scale | Analysis | Decision rule |
|---|---|---|---|---|
| Material screen | Sc x, thickness, sulfur condition, anneal | Fractional factorial or response-surface design; ≥3 independent deposition runs | Mixed-effects model with run as random effect | Advance only phase-stable factors with reproducible electrical effect |
| Electrode mechanism | Pt/Au/Ag/Cu, polarity, compliance | ≥30 valid cells per condition for screening | Distribution plots, effect sizes, bootstrap confidence intervals | Mechanism assignment must survive inert-electrode controls |
| Finalist statistics | Geometry, pulse amplitude/width/count, temperature | ≥100 devices across multiple locations/runs; ≥100 cycles/device for initial CV | Hierarchical device/run model; C2C separated from D2D | Pre-registered acceptance window, not best-device selection |
| Reliability | Stress time, temperature, state, duty cycle | Multiple temperatures and censored failures | Weibull/survival analysis; Arrhenius only if mechanism is stable | Report confidence bounds and failure modes with extrapolation |
| Analog states | Program/read algorithm and target level | Repeated write/read distributions for every claimed state | d′ij = |µi−µj|/√[(σi²+σj²)/2] | Adjacent levels must meet a predefined separation/error-rate criterion |
\[\mathrm{CV}=\frac{\sigma}{\mu}\qquad\vert\qquad F(t)=1-\exp\!\left[-\left(\frac{t}{\eta}\right)^\beta\right]\qquad\vert\qquad \mathrm{AF}=\exp\!\left[\frac{E_a}{k_B}\left(\frac{1}{T_{\mathrm{use}}}-\frac{1}{T_{\mathrm{stress}}}\right)\right]\]
Sample counts above are planning minima, not universal proof thresholds. A power analysis should use pilot variance and the smallest scientifically meaningful effect. For switching probability, logistic or survival models are often more appropriate than comparing only mean VSET.
Electrical protocol
- Instrument correction: open/short compensation, cable capacitance, series resistance, probe contact, bandwidth, trigger skew, and actual device voltage must be measured.
- Read-disturb baseline: choose read voltage from repeated non-destructive reads before interpreting retention or analog state drift.
- Switching map: current-limited I–V followed by pulse amplitude–width–probability maps; report censored non-switching events.
- Plasticity: PPF, STP decay, LTP/LTD, and STDP pulse trains with matched energy controls; count statistically separable states rather than pulses.
- Reliability: retention at multiple temperatures; G14 endurance gate ≥10⁹ cycles, G16/G21 program target ≥10¹⁰ cycles, and exploratory G16 stretch target >10¹² cycles; 4 K → 450 K transport; humidity/oxygen ageing; and later TID campaigns.
- All metrics reported as distributions (cycle-to-cycle and device-to-device), never best-case single-device curves.
1 · MaterialsPhase, composition, interfaces, strain
2 · Single cellAg⁺/Li⁺ pathway separation, pulse response
3 · StatisticsArrays, variability, endurance, retention
4 · Integration1T1R selectors, BEOL budget, system energy
17From Material to Machine: System Architecture
The program sets a geometric density objective of 10¹⁰ synapses/cm² for a 3D crossbar, plus targets of <0.5 pJ per spike and approximately 20 W total chip power. None has been demonstrated by the proposed stack; the density corresponds only to a 100 nm square pitch before selector, routing, via, yield, and stacking overhead.
NEURO-SYNAPSE-OMNI is an event-driven sensory processor, not a general-purpose artificial brain. Sensor events are converted to spikes, processed in memristive crossbar arrays, and returned as classifications, anomaly scores, or control outputs — with minimal data movement.
01
Synaptic cell
Each (Ag,Li)-Te / (Ho,Sc,Ca)₂(S,F)₃ device targets 10-bit analog conductance. A series transistor or selector (1T1R / 1S1R) limits sneak currents in the array.
02
3D crossbar tile
Cells would sit at row–column intersections across vertically stacked planes. Voltages encode activations and column currents can approximate analog multiply-accumulate. The 10¹⁰ synapses/cm² figure is an unachieved geometric objective before selector, interconnect, yield, and stacking overhead.
03
Peripheral circuits
Pulse drivers program weights; integrators, comparators, and ADCs read outputs. Current compliance protects filaments during adaptation events.
04
Learning controller
A digital scheduler applies STDP-compatible pulse trains, compensates drift, and maps weights to conductance. Early prototypes use off-chip-trained weights with on-chip adaptation.
05
System module
Tiles, microcontroller, memory, power management (~20 W target), and sensor interfaces form one deployable module. Digital logic handles supervision, telemetry, and recovery.
Signal path
Sensor event → spike encoder → crossbar tile → current integration → digital decision → actuator or host. Event cameras, vibration sensors, acoustic arrays, and biosignal monitors are the first target applications.
Physical closure register: device to system
| Physical domain | Controlling quantities | Failure if omitted | Required experiment or model | Design response |
|---|---|---|---|---|
| Electric field & electrostatics | Actual device voltage, field concentration, permittivity, interface charge, screening length, space charge and electrode geometry. | Applied voltage is mistaken for uniform active-layer field; edges or contacts dominate switching. | Calibrated I–V/C–V, geometry/thickness series and electrostatic finite-element model with measured ε and contacts. | Round electrodes, field plates, thicker edge dielectric, selector compliance and geometry-normalized comparison. |
| Drift, diffusion & reaction | Mobility, diffusion tensor, activity, field/temperature dependence, transference number and charge-transfer kinetics. | A fitted time constant is incorrectly assigned to Ag, Li or vacancies. | Poisson–Nernst–Planck/reaction model constrained by isotope profiles, impedance, pulse transients and temperature series. | Ion-selective barriers, shorter paths, bounded pulse charge and separate fast/slow devices when coupling is unstable. |
| Electronic transport | Ohmic, Schottky, tunnelling, hopping, Poole–Frenkel or percolative regimes; carrier density and mobility. | Read current changes are labeled ionic memory although contacts, traps or heating explain them. | Temperature/thickness/area/bias-polarity series, Hall where valid, noise spectroscopy and physically compared models. | Choose electrode/barrier and read window from the identified regime; avoid overfitting one I–V curve. |
| Noise & signal integrity | Johnson, shot, generation-recombination, 1/f, random-telegraph and ionic-composition noise; bandwidth and SNR. | Nominal analog levels overlap, events trigger falsely, and claimed bit depth disappears. | Power spectral density versus state, area, bias, temperature and bandwidth plus time-domain threshold-error rates. | Differential read, bandwidth limit, integration, reference cells, coding and precision chosen from measured SNR. |
| Thermal physics | Joule heating, thermal boundary resistance, heat capacity, diffusion length, ambient/cold-stage load and Arrhenius regime. | Thermal switching mimics field chemistry; retention extrapolation crosses a mechanism change; 4 K wiring dominates. | Transient electrothermal model, thermometry or calibrated proxy, pulse-duty sweep and multi-temperature chemistry/transport. | Shorter pulses, heat spreading, thermal isolation where desired, duty cycling and no Arrhenius extrapolation across phase/mechanism changes. |
| Mechanics & microstructure | Stress, adhesion, grain boundaries, texture, roughness, electromigration force, package strain and thermal-expansion mismatch. | Cracks, delamination and grain-specific paths create drift or misleading device-to-device variability. | Wafer bow, stress/adhesion, AFM/TEM/EBSD where suitable, thermal cycling and layout-dependent failure mapping. | Compliant/bonded stack, adhesion/barrier layers, grain control, symmetric layout and stress-aware package. |
| Selector & crossbar non-idealities | Nonlinearity, half-select disturb, sneak current, line R/C, IR drop, fan-in, parasitic capacitance and 1T1R/1S1R area. | Single-cell performance cannot be reproduced in an addressable array. | Measured compact model in SPICE/array solver, line-length sweep, half-select stress, yield/fault map and selector co-test. | Tile-size limit, hierarchical routing, selector co-design, bias scheme, redundancy and local conversion. |
| Converters & mixed signal | DAC/ADC bits, ENOB, sampling/event rate, reference drift, integrator noise, comparator offset and calibration energy. | Peripheral power and error exceed the cell advantage. | Rail-resolved power, converter transfer/noise, end-to-end task accuracy and precision sweep at realistic sparsity/batch. | Analog accumulation, low-resolution/event thresholding, time encoding, shared conversion and workload-specific precision. |
| Timing, routing & synchronization | Spike rate, arbitration, congestion, clock-domain crossing, asynchronous handshake, latency distribution and off-chip bandwidth. | Sparse core stalls at routers or synchronizers; nominal device speed is irrelevant. | Cycle/event-accurate network model validated on FPGA/prototype traffic and worst-case bursts. | Locality-aware mapping, multicast, hierarchical routers, bounded queues and asynchronous islands with explicit synchronization. |
| Variability, ageing & information | C2C/D2D/run variation, drift, retention, endurance, fault correlation, effective bits and mutual information. | Best-device curves overstate array accuracy and lifetime. | Hierarchical statistics, survival/Weibull analysis, drift model, adjacent-state d′ and hardware-in-loop task simulation. | Verify-write, recalibration, fault-aware training, differential encoding, spare rows and binary fallback. |
| Spin, optical & harvesting | Spin transparency/damping, magnon dispersion, optical absorption/emission/loss, quantum efficiency, coupling and harvested-power duty cycle. | G24 transducer overhead overwhelms a useful ionic core. | Separate source-to-detector efficiency, propagation/coupling loss, modulation depth, latency and task-level energy for each link. | Bond only qualified modules; remove channels that do not provide unique function or measured energy–delay gain. |
\[v_{n,\mathrm{rms}}=\sqrt{4k_BTRB}\qquad\vert\qquad i_{\mathrm{shot,rms}}=\sqrt{2qI\Delta f}\qquad\vert\qquad\tau_{RC}=R_{\mathrm{line}}C_{\mathrm{line}}\]
Physics tipA low device write energy is not a low task energy. Use the same accuracy, latency, duty cycle, temperature and workload while counting sensor, encoder, selector, lines, ADC/DAC, calibration, routing, controller, package and idle power.
Operating modes
- Inference target: conductance states should remain stable during low-disturb reads; 0.2 V and sub-picojoule operation require waveform measurements at device and peripheral levels.
- Adaptation hypothesis: selected cells receive controlled pulse trains intended to separate faster Ag-related dynamics from slower Li-related retention.
- Recovery: the controller measures drift, remaps defective cells, and restores weights autonomously.
18Target Markets
🛰️
Space & Defense Research
Potential applications require measured TID and single-event response, thermal-vacuum cycling, vibration, retention, package reliability, and system fault tolerance. Fluorination alone does not establish radiation hardness or eliminate shielding.
❄️
Quantum-Control Research
Operation at 4 K is an unvalidated target. Temperature-dependent transport, local heat load, noise, and qubit-coexistence tests are required before cryostat integration can be claimed.
📱
Edge AI & Robotics
Event-driven in-memory processing could reduce data movement, but autonomy gains require complete module measurements including sensors, converters, control, communications, idle power, and battery capacity.
🫀
MedTech & Wearables Research
Low-voltage targets may be relevant to biosignal processing, but implants additionally require biocompatibility, hermetic packaging, sterilization, safety, long-term reliability, and regulatory qualification.
🚗
Automotive & Avionics Research
Suitability depends on measured automotive or avionics temperature grades, functional-safety architecture, endurance, retention, package stress, radiation environment where relevant, and qualified manufacturing.
📜
IP Development
The proposed materials stack and cell architecture may support patent and licensing work subject to prior-art review, enablement, ownership, freedom-to-operate analysis, and experimental validation.
AAnnexes A0–A7
The annex sequence is intentionally separated from the numbered main narrative; the main sequence resumes at section 19 after A7.
A0Investment Landscape & Market-Value Outlook
Forecast disciplineCommercial market reports use materially different definitions of “neuromorphic computing.” Their values are external scenarios, not audited revenue and not a valuation of NEURO-SYNAPSE-OMNI. Currency, base year, forecast year, scope and publication date must remain attached to every figure.
U.S.-centered market forecasts in USD
| Publisher / geography | Base value | Forecast value | Published CAGR | Scope signal | Interpretation |
|---|---|---|---|---|---|
| MarketsandMarkets, North America, Jun. 2026 | US$10.0M in 2024 | US$439.6M in 2029 | Approximately 113.1% implied for 2024–2029: (439.6 / 10.0)1/5 − 1 | Regional offering, deployment and application scope; includes the United States and Canada | The page also reports 87.8%; that rate is inconsistent with the displayed 2024 and 2029 endpoints, so the implied CAGR is used here |
| Grand View Research, United States | Base value not exposed in the accessible summary | US$5,179.8M in 2030 | 19.8% for 2024–2030 | Broad U.S. neuromorphic-computing revenue definition across components and end uses | United States-specific but substantially broader than a device-only market |
The 2029 North American narrow forecast and 2030 broad United States forecast differ by more than an order of magnitude despite similar geography and timing. This is not statistical uncertainty around one market; it reflects incompatible inclusion rules. NEURO-SYNAPSE-OMNI therefore uses bottom-up U.S. customer, unit, price and qualification assumptions rather than averaging these reports.
Estimated U.S. market value through 2035
Planning extrapolation · not a publisher forecastThe 2035 values below extend the broad U.S. 2030 endpoint of US$5,179.8M using three explicit annual-growth assumptions. They estimate the addressable neuromorphic-computing category, not NEURO-SYNAPSE-OMNI revenue, company valuation, SAM or SOM.
\[V_{2035}=V_{2030}(1+g)^5,\qquad V_{2030}=\mathrm{US\$5.1798\ billion}\]
| Scenario | 2030 anchor | Assumed 2030–2035 CAGR | Estimated 2035 value | Use |
|---|---|---|---|---|
| Conservative | US$5.1798B | 10.0% | US$8.34B | Adoption and qualification slow after 2030 |
| Planning base | US$5.1798B | 15.0% | US$10.42B | Middle case for strategic capacity planning |
| Published-rate continuation | US$5.1798B | 19.8% | US$12.78B | Mechanical continuation of the cited 2024–2030 U.S. CAGR; highest-risk case |
U.S. neuromorphic-computing scenarios to 2035US$ billions
All paths share the cited 2030 anchor; 2031–2035 values are calculated scenarios rather than observed revenue.
NEURO-SYNAPSE-OMNI market-sizing model
\[\mathrm{SAM}_y=\mathrm{TAM}_y\times s_{\mathrm{qualified\ hardware}}\times s_{\mathrm{target\ application}}\times s_{\mathrm{reachable\ geography}}\]
\[\mathrm{SOM}_y=\sum_{p\in\mathrm{products}}\left(\mathrm{qualified\ units}_{p,y}\times\mathrm{net\ price}_{p,y}\right)+\mathrm{license\ revenue}+\mathrm{engineering\ revenue}\]
| Scenario | Evidence assumption | Permitted revenue category | Forecast method | Invalid shortcut |
|---|---|---|---|---|
| Research / downside | G1–G11 generate data but no differentiated array advantage | Sponsored research, characterization, IP options and engineering services | Signed contracts and funded work packages only | Applying a global-market CAGR to project value |
| Niche / base | G12–G21 demonstrate a repeatable advantage in one radiation, cryogenic, sensing or industrial-edge workload | Evaluation kits, prototype modules, non-recurring engineering and field-limited licenses | Qualified customer pipeline × probability × delivery capacity × net price | Counting all edge AI or memory revenue as serviceable market |
| Platform / upside | G22 selector-integrated 3D array and process-module transfer with measured task benefit, yield and second source | Device/module sales, process/IP licensing and design enablement | Bottom-up wafer/die capacity, good-die yield, design wins and royalty-bearing volume | Assuming a fixed market share before product qualification |
| G24 option value | At least one G9/G23 optical, spin or ionic link enables a unique function or improves full-system energy–delay | Strategic joint development, chiplet IP or application-specific system | Risk-adjusted program value by independently funded transducer milestone | Adding photonics, spintronics and neuromorphic TAMs together |
Competitive landscape: 17 actors and controlled access status
Status discipline · verified from public evidence Aug. 8, 2026This register uses only four labels: commercialized, limited commercial access, research only, and not publicly verifiable. A product page, benchmark, funding round, partnership, roadmap, “available” announcement, or contact-sales form does not by itself prove unrestricted ordering or volume shipments. Status describes publicly visible access, not technical merit, revenue, production volume, or company viability.
| Controlled label | Required public evidence | What is not enough |
|---|---|---|
| commercialized | Public purchase/distributor route, shipping production module, or clearly deployed generally available product. | Announcement, “production-ready,” partner logo, product brief, or contact sales alone. |
| limited commercial access | Evaluation hardware, samples, early-access program, developer kit, licensed IP, or customer/partner-gated access. | Does not imply open ordering, volume, profitability, or broad customer deployment. |
| research only | Publicly described laboratory, academic, consortium, or pre-product research program without a commercial offer. | Research deployment is not a customer shipment. |
| not publicly verifiable | Public claims exist, but accessible evidence does not establish either a usable access route or a research-only boundary. | Absence of proof is not proof that no product or customer exists. |
| # / category | Actor & public program | Technical basis | Controlled status | Public evidence supports | Evidence does not support | Benchmark for OMNI |
|---|---|---|---|---|---|---|
| 1 · Direct neuromorphic | Intel · Loihi 2 / Hala Point | Asynchronous event-driven SNN cores, distributed memory/compute and Lava software. | research only | Intel Labs identifies Loihi 2 as a research processor, Hala Point as a neuromorphic research system, and INRC access for qualified groups. | No general product ordering or volume customer shipment. | Sparse event energy, online adaptation, routing scale, software maturity and research reproducibility. |
| 2 · Direct neuromorphic | IBM · TrueNorth / NorthPole | Digital brain-inspired inference with colocated memory/compute and reduced off-chip movement. | research only | Published IBM research chips and peer-reviewed architecture results. | No generally orderable NorthPole/TrueNorth product or public customer-volume evidence. | Energy/latency at matched accuracy without analog drift, forming, or chemical integration. |
| 3 · Direct neuromorphic | BrainChip · Akida | Fully digital sparse/event-driven NPU, on-chip learning and licensable IP/development hardware. | limited commercial access | Silicon, developer community, boards/shop links, software and IP engagement are publicly presented. | Public pages do not establish unrestricted volume availability for every Akida generation or integration. | Developer friction, milliwatt streaming tasks, digital portability and adaptation benefit. |
| 4 · Direct neuromorphic | SynSense · Xylo / Speck | Microwatt SNN sensory processing with event-driven recurrent networks and development kits. | limited commercial access | Xylo IMU/audio kits, datasheets and a sales-linked “Start Experimenting” route. | A sales contact and kit documentation do not prove unrestricted chip volume. | Always-on audio/IMU/biopotential power, latency, software workflow and sensor-interface noise. |
| 5 · Direct neuromorphic | Innatera · Pulsar | Heterogeneous spiking processor plus conventional control/acceleration for sensor-edge workloads. | limited commercial access | Public product/developer and partner positioning supports controlled evaluation or integration access. | “Available” marketing without an open purchase route does not establish general or volume shipments. | Mixed SNN/digital partition, sensor latency, programmability and production integration. |
| 6 · Direct neuromorphic | SpiNNcloud · SpiNNaker2 | Many-core event-based machine for large SNN and hybrid workloads. | limited commercial access | Institutional systems, research deployments and organization-level access are publicly described. | No open module ordering, public unit pricing, or evidence of broad volume shipments. | Neuron/synapse scale, event-routing congestion, programmability and system-level power. |
| 7 · Direct neuromorphic | GrAI Matter Labs · GrAI VIP / NeuronFlow | Event-driven dataflow inference positioned for low-latency edge processing. | not publicly verifiable | Company/product positioning and historical announcements identify the architecture. | Accessible public evidence does not reliably establish present ordering, sampling, or a research-only boundary. | Deterministic latency, compiler/toolchain, workload coverage and availability evidence. |
| 8 · Direct neuromorphic | Rain AI · energy-efficient AI hardware program | Neuromorphic/in-memory hardware R&D; current public page states that the company is building hardware. | research only | An active development program and contact route. | No named generally available product, evaluation kit, public samples or shipments. | Material/device evidence, manufacturable architecture, software path and time to customer-accessible silicon. |
| 9 · Analog / in-memory | d-Matrix · Corsair / JetStream | Digital in-memory compute, chiplets/cards and inference software for generative AI. | limited commercial access | Detailed products, briefs, software and contact-sales/early-access pathway. | Contact sales and projections do not prove open ordering or volume shipments. | Full-card/rack throughput, memory capacity, software deployment and inference economics. |
| 10 · Analog / in-memory | Mythic · M1076 AMP / M.2 cards | Flash-based analog matrix processing with compute and weight storage colocated. | not publicly verifiable | Named silicon/cards, specifications and product documentation. | Current pages do not show an unrestricted purchase route or independently establish present customer shipments. | Analog accuracy, endurance, model support, converter overhead and module availability. |
| 11 · Analog / in-memory | Aspinity · AML100 / AML200 | AnalogML sensing before the ADC; AML100 always-on analog classification and AML200 RF test-chip path. | limited commercial access | AML100 is described as a production IC shipping today, with SDK and “evaluate & build” contact route; AML200 is identified as in development. | No open order, price, volume, or general availability proof for the complete portfolio. | Sensor-to-decision energy, avoided ADC cost, input noise/bandwidth and field programmability. |
| 12 · Analog / in-memory | EnCharge AI · EN100 / analog in-memory platform | Capacitor-based analog in-memory compute with edge-to-cloud form-factor roadmap. | not publicly verifiable | Measured-silicon claims, technology description, roadmap and get-started contact are public. | No public unrestricted order route or shipment/volume evidence for the named accelerator. | Precision robustness, process portability, software, total inference energy and access. |
| 13 · Analog / in-memory | TetraMem · analog in-memory platform | Compute-at-data analog architecture for low-power on-device AI. | not publicly verifiable | Product/technology positioning and company activity. | No accessible named orderable device, evaluation terms, shipping evidence, or explicit research-only boundary. | Silicon proof, programmable precision, endurance/variation management, toolchain and access. |
| 14 · Edge-AI substitute | NVIDIA · Jetson Orin / Thor | GPU/NPU heterogeneous modules with CUDA-X and JetPack for robotics and edge inference. | commercialized | Official “Buy” route, production modules, developer kits, software and distributor/partner ecosystem. | GPU availability does not prove neuromorphic or in-memory efficiency for sparse temporal workloads. | Time-to-deploy, model breadth, throughput, thermal design, software ecosystem and total module cost. |
| 15 · Edge-AI substitute | Qualcomm · Dragonwing / Snapdragon platforms | Heterogeneous CPU/GPU/Hexagon NPU SoCs deployed through devices, modules and OEM channels. | commercialized | Active production processors, device finder, hardware-provider ecosystem and shipping OEM products; individual SKUs may still be sampling. | Portfolio commercialization does not mean every announced IQ device is in volume or openly orderable. | Industrial temperature, safety, connectivity, OEM scale, NPU efficiency and ecosystem. |
| 16 · Edge-AI substitute | Hailo · Hailo-8 M.2 | Dataflow edge inference accelerator with compiler/software and standard modules. | commercialized | Official page provides global distributor links for small online quantities and bulk orders. | Published TOPS alone does not establish application accuracy, latency or energy versus OMNI. | Orderability, industrial range, standard form factor, compiler coverage and task energy. |
| 17 · Edge-AI substitute | Google · Coral / Edge TPU platform | Edge tensor acceleration plus evolving compiler, reference-design and RISC-V hardware platform. | commercialized | Established accelerator/dev-board product lineage and current public developer platform/reference designs. | Current platform documentation does not guarantee stock or lifecycle for every legacy Coral SKU. | Developer accessibility, quantized-model workflow, ecosystem, module cost and lifecycle. |
Public-access status of 17 benchmark actorspublic evidence
Counts are generated from the controlled-status column above and update with the table.
Comparison tipDo not rank unlike chips by TOPS/W alone. Fix the model, dataset, accuracy, batch, sparsity, latency, temperature, host CPU, memory, converters, software version and wall-plug boundary; then report uncertainty and product-access status separately.
Competitive design lessons for NEURO-SYNAPSE-OMNI
Win on a bounded workload
Direct neuromorphic products emphasize sparse temporal sensing. The first OMNI proof should therefore be one audio, vibration, event-vision or biosignal task, not a claim of universal AI superiority.
Software is part of the device
Akida, Xylo, Jetson, Hailo and Coral expose models, compilers, SDKs and boards. A chemically novel synapse needs a compact model, calibration API, reproducible training flow and evaluation hardware before customers can test it.
Beat the whole module
A materials advantage must survive selector, routing, ADC/DAC, host, package, cooling and idle power. Commercial edge modules are the procurement baseline even when their physics is less novel.
Observable U.S. capital signals in USD
| Signal | Publicly reported amount | Scope | Relevance / limitation |
|---|---|---|---|
| CHIPS for America | US$11B R&D and US$39B manufacturing incentives | U.S. semiconductor R&D ecosystem plus domestic facilities and equipment | National infrastructure scale; no amount is committed to this project |
| NSTC / Natcast, Jan. 2025 | Up to US$6.3B under a long-term NIST agreement | Operate the U.S. National Semiconductor Technology Center and support research, prototyping and scale-up | Potential U.S. ecosystem pathway subject to membership, calls and eligibility; not project revenue |
| NIST NAPMP | Approximately US$3B program; US$300M finalized in first advanced-substrate awards | U.S. advanced packaging materials, substrates, process, photonics, chiplets and pilot transition | Relevant to heterogeneous G22–G24 transfer, but awards to other recipients are not available project cash |
| Rain AI Series A, Feb. 2022 | US$25M | U.S. neuromorphic accelerator development, engineering-team expansion and prototype advancement | Closest private neuromorphic-stage comparable; technology, maturity and capital needs still differ |
| d-Matrix Series B, Sep. 2023 | US$110M | Santa Clara digital in-memory-compute chiplet commercialization and recruitment | Product-stage memory-centric compute comparable, not a valuation proxy for an unfabricated material stack |
| EnCharge AI Series B, Feb. 2025 | >US$100M; reported cumulative funding >US$144M | Santa Clara analog in-memory-computing accelerator commercialization and product roadmap | Shows U.S. capital after multiple research chip generations and product evidence |
Government grants, contributions & tax incentives
Funding boundary · verified Aug. 8, 2026The entries below are application pathways, not awards, receivables, or committed project cash. Program rules, calls, appropriations, national-security review, stacking limits, eligible costs, and deadlines can change. Budget a government contribution only after a signed agreement; record a tax credit only against eligible incurred expenditure using advice from the responsible agency and a qualified tax professional. Canadian and U.S. routes require different eligible entities and domestic work.
| Program / jurisdiction | Mechanism & published scale | Who applies | Best NEURO-SYNAPSE-OMNI fit | Immediate application package | Critical restriction | Official source |
|---|---|---|---|---|---|---|
| NRC IRAP · Canada | Advisory services, connections, and non-dilutive project funding; amount is assessed case by case. | Innovative, growth-oriented Canadian small or medium-sized business incorporated and operating in Canada. | G10–G16 materials/device feasibility, Canadian technical hires, IP planning, and first commercial demonstrator. | Canadian company profile, technical uncertainty, 12–18 month work plan, payroll/vendor budget, commercialization case, and request for an Industrial Technology Advisor. | Contact IRAP before committing costs; eligibility and project approval are not automatic, and program administration may transition to the Canada Innovation Corporation. | NRC IRAP [26] |
| NSERC Alliance Advantage · Canada | C$20,000–1M/year for 1–5 years; NSERC contribution is 66.7% of shared direct project costs. | Eligible Canadian university researcher with at least one active partner recognized for cost sharing; funds flow to the university. | G1–G21 materials, mechanism, reliability, compact models, trainee development, and independent replication. | Named professor, partner cash and in-kind commitment, research agreement/IP schedule, proposal, training plan, budget, benefit-to-Canada case, and research-security forms. | Not a grant paid to the company; no secret or contract research, partner cash is required, and sensitive semiconductor work can trigger NSGRP/STRAC review. | NSERC Alliance [27] |
| CFI Innovation Fund 2027 · Canada | Competition budget up to C$325M; CFI funds up to 40% of eligible infrastructure cost, plus an associated operating envelope. | Eligible Canadian institution submits; the company may participate as an industrial user or partner but is not the direct applicant. | Shared deposition, lithography, microscopy, cryogenic, reliability, or packaging infrastructure supporting G1–G24. | Join a university/core-facility proposal with a >C$1M infrastructure plan, utilization forecast, complementary financing, governance, and national benefit. | Notice of intent is due Sep. 29, 2026 and proposals Feb. 2, 2027; this is infrastructure funding, not startup operating cash. | CFI Innovation Fund [28] |
| FABrIC Challenge Funding · Canada | Call-based semiconductor challenge funding under a federal Strategic Response Fund initiative managed by CMC Microsystems. | Eligible Canadian semiconductor ecosystem teams under the terms of each challenge call. | G9/G19/G22–G24 chip design, photonics/MEMS/compound-semiconductor integration, prototyping, commercialization, and talent. | Become a member, map the project to an open challenge, identify Canadian design/fabrication partners, define domestic economic benefit, milestones, and matching resources. | No generic amount or open deadline should be assumed; use only the active call guide and preserve foreground/background IP terms. | FABrIC [29] |
| PRIMA Québec · Quebec | Call-based R&D financing and consortium support for advanced materials; contribution and cost-share vary by program. | Quebec company working with eligible academic/research partners under the selected call. | G10–G21 chalcogenide/ionic films, interfaces, metrology, scale-up, and industrial validation. | Request a fit review; prepare a Quebec industrial lead, research partner, materials innovation, work packages, IP plan, quotations, and commercialization benefits. | PRIMA is a sector intermediary, not evidence of a provincial award; verify membership, partner, stacking, expenditure, and call-closing rules. | PRIMA funding programs [30] |
| Strategic Response Fund · Canada | Repayable or non-repayable support negotiated for large-scale, transformative projects in strategic sectors and supply chains. | Eligible Canadian for-profit, non-profit, cooperative, academic, or network applicant according to the selected stream and project requirements. | G19–G22 pilot line, Canadian semiconductor supply chain, advanced manufacturing, AI infrastructure, major commercialization, and jobs. | Use the eligibility checker, request a consultation, and prepare a large project with financing plan, Canadian benefits, jobs, supply-chain resilience, technical diligence, and quantified milestones. | Former SIF branding has changed; this is generally not the first source for a laboratory concept, and support type/amount follow diligence and negotiation. | ISED SRF [31] |
| SR&ED · Canada | Federal deduction and investment tax credit for eligible Canadian scientific research and experimental development expenditure. | Corporation, individual, trust, or partnership conducting and documenting eligible work in Canada; claim accompanies the tax return. | Cross-cutting recovery against eligible experimental salaries, materials, and other permitted costs from G1 onward. | Maintain contemporaneous hypothesis, uncertainty, experiment, result, time, material, contract, assistance, and expenditure records; obtain pre-claim guidance where useful. | A tax incentive is not an upfront grant; other government assistance can reduce the SR&ED expenditure pool, and technical eligibility alone does not make every cost claimable. | CRA SR&ED [32] |
| NSF America’s Seed Fund · United States | SBIR/STTR non-dilutive seed funding advertised up to US$2M, with no government equity claim. | Eligible U.S. small business; ownership, principal-investigator employment, place-of-performance, and STTR research-partner rules apply. | U.S.-executed G10–G21 deep-tech proof, prototype, commercial validation, and transition to follow-on private capital. | Form a genuinely eligible U.S. applicant, submit a project pitch, then a proposal with technical innovation, R&D plan, team, commercialization, budget, and company registrations. | A Canadian company cannot treat this as directly available cash; do not create a nominal U.S. entity or route foreign work around eligibility and foreign-disclosure rules. | NSF Seed Fund [33] |
| DOE SBIR/STTR · United States | Competitive non-dilutive awards for eligible small businesses responding to Department of Energy mission topics. | Eligible U.S. small business; STTR includes a qualifying U.S. research institution and all work must follow the solicitation. | G12/G19/G21 energy-aware compute, G15 harsh-environment operation, cryogenic controls, materials science, and energy-efficient AI where a live topic matches. | Monitor current topics, establish U.S. eligibility and registrations, identify a national-lab/university role if useful, and quantify DOE mission impact plus commercialization. | Technology relevance is insufficient without an open topic and compliant U.S. entity; reauthorization does not guarantee a suitable solicitation or award. | DOE SBIR/STTR [34] |
| CHIPS R&D CRDO BAA · United States | Rolling Broad Agency Announcement for U.S. microelectronics research, prototyping, and commercial solutions; project budgets should generally be at least US$10M. | Eligible applicant proposing U.S.-based impact and satisfying the BAA, security, domestic-production, and commercial-viability requirements. | Consortium-scale G19–G22 process transfer, metrology, advanced packaging, AI hardware commercialization, or a separately qualified G24 tile. | Build a U.S. consortium and submit a white paper with national/economic-security case, milestones, facilities, workforce, commercialization, domestic production, cost, and technology-protection plan. | Earlier CARISSMA and second NAPMP competitions were closed without awards; use the current BAA only. A meritorious white paper merely enables further negotiation. | NIST CHIPS R&D [35] |
Recommended funding stack: begin with NRC IRAP plus a university-led NSERC Alliance package and disciplined SR&ED records; add PRIMA or FABrIC only when a matching call is open; use CFI for institution-owned shared infrastructure; approach the Strategic Response Fund after a Canadian pilot consortium and private co-financing exist. Treat U.S. SBIR/STTR and CHIPS routes as a separate U.S. execution strategy, not as substitutes for Canadian eligibility.
Investment sequence and value-inflection gates
| Financing stage | Capital purpose | Value-inflection evidence | Best-fit capital | Do not finance yet |
|---|---|---|---|---|
| Pre-seed / non-dilutive research | G1 reference, G2 film, controls, EHS, data system and initial IP search | Repeatable film plus falsifiable switching dataset across ≥3 runs | Research grants, shared infrastructure, founder/angel capital and sponsored projects | Dedicated pilot equipment before host feasibility |
| Seed / translational | G10–G16 mechanism attribution, selector coupons and customer workload definition | Statistically significant advantage over the matched G1/G4/G10 control plus two qualified application partners | Deep-tech seed, strategic semiconductor investors, challenge funding and joint development | Volume forecast without wafer yield and customer acceptance criteria |
| Series A / pilot | G19–G22 down-selection, 200 mm process learning, array demonstrator and compact model | Selector-integrated task benefit, contamination route, second source and reproducible yield trend | Strategic VC, corporate venture, public co-investment and foundry/package partner | G24 heterogeneous integration before component qualification |
| Scale / licensing | Qualification lots, PDK, reliability, customer design wins, packaging and supply contracts | Good-die economics, field data, signed design wins and transferable process control | Growth capital, customer prepayment, license partners and manufacturing finance | Commodity-capacity build without defensible niche margin |
| G24 consortium option | Separate G9 optical, G23 spin and harvesting modules followed by bonded tile | One transduction link with measured system advantage | Mission-led consortium, strategic grants and application partner funding | Single-company full-stack capital commitment at concept stage |
ROI, NPV, IRR & payback framework
ROI boundaryAll internal accounting and investment outputs use U.S. dollars (USD) and a stated valuation date. ROI is an output of evidence-backed cash flows, not a market-growth proxy. The model separates grants from investor capital, excludes sunk costs from forward decisions, and states whether U.S. federal/state tax, dilution, terminal value and inflation are included.
\[\mathrm{FCF}_t=\mathrm{cash\ revenue}_t-\mathrm{cash\ OPEX}_t-\mathrm{CAPEX}_t-\mathrm{tax}_t-\Delta\mathrm{working\ capital}_t\]
\[\mathrm{ROI}=\frac{\sum \mathrm{cash\ inflows}-\sum \mathrm{cash\ outflows}}{\sum \mathrm{cash\ outflows}}\]
\[\mathrm{NPV}(r)=\sum_{t=0}^{T}\frac{\mathrm{FCF}_t}{(1+r)^t},\qquad \mathrm{NPV}(\mathrm{IRR})=0\]
\[\mathrm{Break\!\text{-}even\ units}=\frac{\mathrm{annual\ fixed\ cash\ cost}}{\mathrm{net\ selling\ price}-\mathrm{variable\ cost\ per\ shipped\ unit}}\]
\[\mathrm{Risk\!\text{-}adjusted\ NPV}=-I_0+\sum_{t=1}^{T}\frac{P(\mathrm{reach\ stage}\ t)\,\mathrm{FCF}_{t\mid\mathrm{reach}}}{(1+r)^t}\]
| ROI view | Required inputs | Decision output | Principal sensitivity | Interpretation limit |
|---|---|---|---|---|
| R&D learning return | Stage cost, probability of technical success, time to evidence, reusable IP/data and scale-up cost avoided by an early stop | Expected value of information and cost per closed uncertainty | Probability update after each replicated experiment | A failed hypothesis can have positive learning value but is not commercial revenue |
| License model | Upfront payment, milestones, royalty rate, licensee net sales, legal/patent cost and probability-adjusted launch date | NPV, IRR, payback date and minimum royalty needed to clear the hurdle rate | Design-win probability, launch delay and royalty-bearing volume | Signed terms replace market-share assumptions; a memorandum is not booked revenue |
| Fabless product model | NRE, wafer and package quotations, die area, gross and mapped yield, test cost, ASP, returns, inventory and support | Contribution margin, break-even units, cash runway and NPV | Good-die yield, package yield, ASP erosion and customer concentration | Gross margin must include known-good-die loss, test and warranty exposure |
| Process-module transfer | Pilot qualification cost, transfer engineering, tool/contamination changes, license fees and foundry volume | Cost per qualified process, royalty break-even and partner economics | Qualification delay, utilization and second-source readiness | Public infrastructure support is not project cash until awarded and contracted |
| G24 strategic option | Module-specific spend, conditional success probability, partner contribution and incremental system value over the G21/G22 electrical baseline | Risk-adjusted NPV of each transducer option and maximum rational next-stage spend | Compound yield and probability that task benefit survives system integration | Do not assign terminal value to unvalidated spin/optical/ionic coupling |
Scenario sheet and investment decision rules
| Case | Inputs to vary together | Mandatory outputs | Decision rule |
|---|---|---|---|
| Downside | Longer qualification, lower yield and ASP, no grant, one delayed customer, higher package/test cost and no terminal value | Runway, peak cash need, loss at stop gate, NPV and recoverable IP/equipment value | Stop or redesign when the next experiment cannot restore positive risk-adjusted NPV within the approved capital envelope |
| Base | Measured yield trend, current quotations, probability-weighted pipeline, contracted grant assumptions and conservative ramp | NPV at the approved discount rate, IRR, payback, break-even units and financing need by gate | Advance only when technical and commercial gates are both met and funding covers the next evidence milestone plus contingency |
| Upside | Faster transfer, second source, multiple design wins, licensing income and higher utilization, each tied to explicit evidence | Capacity constraint, working-capital need, dilution requirement and upside NPV | Use for capacity planning, not as the investment case or headline valuation |
| Sensitivity / stress | One-way and combined changes in yield, price, volume, launch date, CAPEX, discount rate and technical-success probability | Tornado ranking, break-even value for each driver and probability of negative NPV | Fund the experiment or contract that reduces the highest decision-relevant uncertainty per dollar |
The investment committee should receive a versioned cash-flow workbook with source links for every quotation or contract, explicit downside/base/upside assumptions, no double counting between grants and private capital, and a reconciliation from technical gates to probability updates. ROI, IRR and payback must always be reported together with NPV and peak cash requirement: each metric alone can rank projects incorrectly.
Investor diligence dashboard
TechnicalReplicated effect size, mechanism bounds, array yield, reliability and task benefit
CommercialNamed workload, paid evaluations, design wins, net pricing and replacement trigger
IndustrialProcess route, contamination acceptance, second source, package and good-die cost
FinancialMilestone runway, quotation-backed use of funds, dilution, scenario cash flow and stop rules
Valuation boundaryNo enterprise valuation is inferred here. A defensible project valuation requires ownership/capitalization data, validated IP, milestone probability, cash needs, customer evidence, comparable transactions and a risk-adjusted financial model. Market size alone is not valuation.
A1Product Requirements & Use Cases
Requirements ruleA material metric becomes a product requirement only when it is tied to a workload, operating envelope, measurement method, baseline, and pass/fail threshold. Values below define qualification questions; they are not measured capabilities.
| Use case | Reference workload | Required evidence | System acceptance gate | Explicit non-goal |
|---|---|---|---|---|
| Industrial edge anomaly detection | Event-driven vibration or acoustic classification with bounded sensor rate and latency | Task accuracy, false-alarm rate, end-to-end energy, drift, update frequency, and temperature dependence | Statistically exceeds a declared digital or G1 baseline in energy–delay at matched accuracy and duty cycle | General-purpose AI replacement |
| Radiation-aware sensing research | Fixed inference/adaptation task before, during, and after declared TID and particle exposure | Parametric drift, functional failures, retention, recovery, package response, and confidence intervals | Meets a mission-specific error budget after device, peripheral, and controller effects are included | Intrinsic radiation hardness inferred from fluorine content |
| Cryogenic control research | Low-rate temporal filtering or calibration task at specified cryostat stages | Temperature-dependent transport, noise spectrum, local heat load, cooldown repeatability, and wiring overhead | Useful operation at the declared temperature with measured cold-stage power below the allocated thermal budget | Compatibility with qubits inferred from a 4 K device test |
| Biosignal and wearable research | ECG, EMG, or neural-event classification using a public or governed dataset | Sensitivity, specificity, latency, energy, subject-level validation, drift, packaging, and safety assessment | Matched task benefit plus an application-specific biocompatibility and regulatory development plan | Implant readiness from low switching voltage alone |
Cross-cutting requirement hierarchy
1 · MissionWorkload, environment, duty cycle, lifetime, safety, and acceptable failure
2 · SystemAccuracy, latency, throughput, energy, thermal load, availability, and interfaces
3 · ArrayYield, selector margin, drift, conductance range, update precision, and fault mapping
4 · DeviceWaveforms, variability, retention, endurance, mechanism, geometry, and environment
A2Evidence Dashboard, Readiness & Benchmark Protocol
Current results register
| Scope | Current evidence in this dossier | Status | Evidence required to advance |
|---|---|---|---|
| G1 oxide reference | Established literature platform; no local dataset reported | Reproduce locally | Raw pulse/I–V data, wafer map, ≥3 process runs, device/cycle distributions, retention and endurance |
| G10/G14 sulfide host | Ho₂S₃ compound precedent and ionic-radius calculation; no cited switching result for the proposed films | Hypothesis | Phase/composition, inert-electrode switching controls, mechanism evidence, analog-update statistics |
| G3/G4/G12–G18 active-metal and doped cells | ECM/CBRAM physical precedent in other chalcogenides; proposed stacks not fabricated | Architecture target | Factorial electrode/reservoir/dopant controls and statistically superior exit metric versus the appropriate control |
| G21 co-ionic cell | Conceptual assignment of fast Ag- and slower Li-related state variables | Unvalidated concept | Ag-only, Li-only and full-stack operando attribution with separable timescale distributions |
| G24 heterogeneous system | Constituent phenomena have precedent in other material platforms; complete path unbuilt | Frontier concept | Separate component qualification followed by pairwise transduction and task-level benefit |
| Numerical performance figures | Design targets, illustrative scenarios, or literature context unless a dataset is explicitly linked | Not local measurements | Versioned data, geometry, waveform, environment, sample size, uncertainty, analysis code and provenance |
Provisional readiness gates
These internal gates are inspired by technology-readiness practice but are not a certified TRL assessment.
| Gate | Meaning | Required artefact | Applicable generations |
|---|---|---|---|
| R0 · Principle | Mechanism and falsifiable hypothesis defined | Prior-art map, governing equations, controls, predicted signatures, stop criteria | Unfabricated G1–G24 concepts |
| R1 · Material | Repeatable film and interfaces | Three-run phase, thickness, composition, roughness and environmental-stability distributions | Entry gate for every new composition |
| R2 · Device | State change is repeatable and mechanism-bounded | Matched controls, pulse statistics, retention, endurance, disturb and failure analysis | Every down-selected G1–G21 cell |
| R3 · Array | Selector-integrated function survives scaling | Yield map, line/selector model, half-select tests, calibration, task inference and full energy | Selected G1–G22 modules |
| R4 · Relevant demonstrator | Packaged system meets a declared use case | Environmental test, baseline comparison, reproducible workload and independent review | Industrial bridge or G24 tile |
Matched benchmark protocol
| Comparison layer | Required baselines | Controlled variables | Reported outputs |
|---|---|---|---|
| Material/device | Local HfOx G1; inert-electrode host; active-metal control; previous generation | Area, thickness, electrode, compliance, waveform, temperature, bandwidth and read protocol | Full distributions, failures/censoring, confidence intervals, mechanism signatures and raw waveforms |
| Memory technology | Published or procured oxide RRAM, CBRAM, PCM and MRAM classes with source and process disclosed | Equivalent state count, retention class, endurance definition, access device and operating environment | Energy, latency, area, drift, variability, endurance and manufacturability without cross-paper cherry-picking |
| Array/system | Digital accelerator and G1 crossbar at matched model, dataset, accuracy and duty cycle | Converters, drivers, communication, calibration, idle power, batch size and fault tolerance | Task energy, latency, throughput, accuracy, thermal load, availability and bill-of-material assumptions |
| Reproducibility | Blind rerun by a second operator, tool, wafer location or partner laboratory | Frozen protocol, randomized sample order, calibration standards and analysis version | Effect size, inter-run variance, deviations, negative results and replication outcome |
A3Risk Register & FMEA
Priority is qualitative until occurrence and detection rates are measured. Owners are roles, not named commitments.
| Failure mode | Effect | Priority | Detection | Mitigation | Owner | Stop / fallback trigger |
|---|---|---|---|---|---|---|
| Ho₂S₃ phase or stoichiometry instability | No reproducible host or uncontrolled leakage | Critical | XRD, XPS, RBS/ERDA, SIMS, thickness and capped/uncapped witnesses | Sulfur overpressure, lower thermal budget, encapsulation and oxysulfide/bilayer split | Materials lead | Terminate pure-host route after two learning cycles without repeatable phase and electrical window |
| Ag filament overgrowth | Hard shorts, abrupt SET and endurance loss | High | Current transients, post-mortem TEM/EDS, failure-map clustering | 1T1R compliance, charge-limited pulses, reservoir/barrier optimization | Device lead | Use nanoclusters, Cu, or a separate volatile device if analog window remains absent |
| Ag/Li pathway non-separability | G21 cannot provide controllable dual timescales | Critical | Factorial controls, isotopic/depth profiling, decay-model comparison | Sequential pulse protocol, blocking interfaces and reduced composition space | Mechanism lead | Adopt the paired G19 compound synapse |
| BEOL contamination or thermal incompatibility | Foundry transfer blocked | Critical | Blanket-wafer diffusion, outgassing, chamber and wafer-edge contamination monitors | Dedicated modules, barriers, heterogeneous bonding and industrial bridge materials | Integration lead | Move new chemistry off-chip or to bonded chiplet |
| Peripheral energy dominates | Device advantage disappears at task level | High | Rail-resolved power and waveform integration by block and operating mode | Lower-resolution conversion, event sparsity, analog accumulation and duty cycling | System lead | Stop custom material scaling if no task energy–delay benefit over G1/digital baseline |
| Single-source critical material | Schedule, cost or sovereignty failure | Medium–high | Supplier audit, lot certificates, capacity/lead-time tracking | Second source, recovery/recycling, lower-loading design and substitute qualification | Supply lead | Freeze scale-up until qualified continuity or redesign exists |
| Optical/spin transduction loss | G24 complexity adds no useful function | High | Calibrated source-to-output energy, loss and latency budget | Qualify modules independently and integrate one link at a time | G24 systems lead | Retain electrical ionic core with optional photonic I/O only |
A4Techno-Economics, IP & Freedom to Operate
Cost model
\[\mathrm{Cost\ per\ shipped\ good\ unit}=\frac{C_{\mathrm{processed\ wafer}}+C_{\mathrm{allocated\ mask/tool/NRE}}+C_{\mathrm{wafer\ probe}}}{N_{\mathrm{known\ good\ dies}}}+\frac{C_{\mathrm{assembly/package}}+C_{\mathrm{final\ test}}}{Y_{\mathrm{package}}Y_{\mathrm{final\ test}}}\]
\[\mathrm{Cost\ per\ usable\ synapse}=\frac{\mathrm{cost\ per\ shipped\ good\ unit}}{\mathrm{physical\ cells}\times\mathrm{mapped\ cell\ yield}\times\mathrm{usable\ state\ fraction}}\]
Wafer-level costs are divided by known-good dies; per-unit assembly, packaging and final-test costs are yield-adjusted separately. This avoids dividing a per-die package cost by the wafer die count or counting the same yield loss twice.
| Scenario | Cost drivers | Required inputs | Decision output |
|---|---|---|---|
| University / shared-facility coupons | Minimum lot charges, targets/precursors, characterization access and operator time | Actual quotations, run count, sample count, metrology hours and failure allowance | Cost per learning cycle and per statistically useful device |
| 200 mm pilot module | Dedicated chambers, masks, contamination controls, low utilization, wafer test and packaging | Route steps, cycle time, uptime, consumables, labor, NRE and measured yield | Cost per good die, break-even volume and dominant yield sensitivity |
| Heterogeneous G24 tile | Known-good dies, bonding, alignment, optical/spin components and compound yield | Module yields, bond yield, test coverage, rework and package losses | Cost and task benefit versus electrical G21 and commercial baseline |
No cost, market size, or margin is claimed until supplier quotations, measured yields, die area, process flow and deployment volume are versioned. Sensitivity analysis must vary yield, tool utilization, Te/Sc/Ho price, layer count and package yield rather than report one-point forecasts.
IP and FTO workstream
| Potential claim family | Enabling evidence needed | Prior-art/FTO search domain | Protection alternative |
|---|---|---|---|
| Composition and layer stack | Fabricated examples, composition ranges, controls and unexpected technical effect | CBRAM, chalcogenide electrolytes, Ag/Li/Te reservoirs, rare-earth sulfides and fluorosulfides | Patent only after enablement; otherwise confidential know-how |
| Pulse protocol and state separation | Reproducible Ag/Li timescale attribution and task benefit | Multi-timescale memristors, compound synapses, verify-write and temporal learning | Software copyright, trade secret, or patent depending on the disclosure strategy |
| Process integration | Barrier, low-temperature deposition, contamination and yield data | BEOL RRAM modules, bonding, encapsulation and active-metal barriers | Process know-how plus narrowly enabled patent claims |
| G24 transduction architecture | Measured spin/optical/ionic coupling with net system benefit | Magnonic-photonic-neuromorphic systems, topological interfaces and in-sensor computing | System architecture claims only after component feasibility |
Legal boundaryThis dossier identifies technical IP questions only. Patentability, inventorship, ownership and freedom to operate require jurisdiction-specific searches and qualified counsel before publication or commercialization.
A5EHS, Standards, Regulation & Security
Environment, health and safety
| Hazard class | Relevant materials/process | Required controls | Evidence before scale-up |
|---|---|---|---|
| Reactive/toxic precursors | Sulfide and fluoride precursor routes; Li-containing sources | Substitution review, closed delivery, gas detection, ventilation, abatement, compatible PPE and emergency plan | Current SDS, institutional process-hazard review, exposure/abatement verification and trained operators |
| Metal and nanoparticle waste | Ag, Te, Ho, Er, Sc, Bi and contaminated wipes/targets | Segregated collection, traceable hazardous-waste route and recovery feasibility | Mass balance, waste classification, licensed disposal/recycler and spill procedure |
| Vacuum/plasma/laser/cryogenic tools | Deposition, etch, optical G9 and low-temperature testing | Interlocks, lockout, laser classification, oxygen-deficiency monitoring and pressure safety | Tool acceptance, preventive maintenance, training and incident-response drill |
| Environmental footprint | Critical materials, cleanroom energy, process gases, yield loss and packaging | Cradle-to-gate inventory and functional-unit comparison | Energy/material/waste per good die and per task, including recycling assumptions |
Standards and regulatory pathway
| Domain | Candidate framework | Program action | Boundary |
|---|---|---|---|
| Semiconductor reliability | Applicable JEDEC methods and customer-specific qualification | Create a requirements-to-test matrix for retention, endurance, package stress and failure analysis | Method selection depends on product and cannot certify a novel memory by analogy |
| Automotive / industrial safety | AEC-Q100 where applicable; ISO 26262 system lifecycle | Define safety goals, diagnostic coverage, fault injection and traceability with the target customer | Device qualification alone does not establish functional safety |
| Avionics / space | Mission-specific radiation, thermal-vacuum, vibration and electronic-assurance plans | Tailor exposure spectra, lot acceptance, derating and fault-tolerant control | No universal “space qualified” label follows from one TID test |
| Medical research | ISO 14971 risk management; biocompatibility/electrical/software standards as product scope requires | Establish intended use, contact category, safety architecture and regulated design controls | The present research device is not a medical product |
| Management systems | ISO 9001-style document/change control; laboratory competence practices | Calibrations, training, nonconformance, corrective action and controlled records | Certification is a separate organizational process |
Security and fault tolerance
| Threat/fault | Detection | Mitigation | Verification |
|---|---|---|---|
| Weight tampering or malicious programming | Authenticated command log, conductance attestation and anomaly detection | Secure boot, signed models, access control, write-rate limits and protected update modes | Penetration test and unauthorized-pulse fault campaign |
| Drift, stuck cells and read disturb | Reference cells, parity/checksums, periodic readback and health telemetry | Redundant mapping, sparing, verify-write, calibration and graceful degradation | Accelerated drift/disturb tests plus injected fault maps at task level |
| Side-channel leakage | Power, timing, electromagnetic and optical correlation analysis | Scheduling, shielding, randomized operations and partitioned sensitive weights | Attack-specific leakage assessment on the packaged system |
| Radiation or transient upset | Error counters, watchdogs, duplicate computation and state scrubbing | ECC/redundancy, hardened controller, checkpointing and safe-state recovery | Fault injection correlated with physical exposure results |
A6Program Governance, Team, Budget & Reproducibility
Work packages and decision rights
| Work package | Accountable role | Core deliverable | Independent review gate |
|---|---|---|---|
| WP1 · Materials | Materials/process lead | Qualified films, interfaces, precursors, controls and EHS package | Phase/composition reproducibility and approved process hazard review |
| WP2 · Device physics | Device/mechanism lead | Factorial test structures, compact hypothesis set and failure analysis | Blinded statistical review against pre-registered exit metrics |
| WP3 · Arrays and circuits | Integration/circuit lead | Selector tile, drivers/readout, variability model and test access | Array yield, disturb, calibration and energy audit |
| WP4 · Algorithms and systems | System/ML lead | Frozen workloads, baselines, hardware-aware training and task results | Matched accuracy/energy/latency review with reproducible code |
| WP5 · Industrialization | Manufacturing/supply lead | Foundry route, suppliers, economics, quality and qualification plan | Transfer-readiness audit and customer requirement review |
| WP6 · Assurance and IP | Program assurance lead | Risk register, standards, security, data governance and IP decisions | Quarterly red-team review; counsel review before disclosure |
Staged budget forecast
U.S. planning basisThis is a fresh bottom-up operating forecast in constant 2026 U.S. dollars, not a foreign-exchange conversion, supplier quotation, grant award or financing commitment. It assumes a U.S.-based core team, fully burdened U.S. compensation, shared university/national-laboratory infrastructure, external U.S. foundry and packaging services, and no owned pilot fab. Each range includes a 25% phase contingency and excludes financing cost, acquisitions, volume-production inventory and construction of a dedicated semiconductor facility.
| Phase / timing from authorization | Generations and scope | Planning envelope | Principal uses of funds | Release gate |
|---|---|---|---|---|
| P0 · Definition, 0–6 months | G1 design, G2 process hazard review, U.S. requirements, controls, IP landscape and supplier quotations | US$0.35–0.85M | 2–4 FTE-equivalents, design, EHS, initial targets/precursors, facility onboarding, data system and U.S. counsel | Approved experiment matrix, process route, safety package and quotation-backed P1 forecast |
| P1 · Material/device proof, 6–18 months | G1–G2 controls, film development, MIM coupons and mechanism screening | US$1.20–2.80M | U.S. personnel, deposition access, materials, masks, microscopy/spectroscopy and electrical statistics | Repeatable host and switching result across at least three independent runs |
| P2 · Composition down-select, 18–30 months | G4/G12/G14 Ag/Te/Sc factorial studies, pulse models, selector coupons and U.S. application baselines | US$2.50–6.00M | Expanded team, factorial lots, advanced chemical analysis, compact modeling, test automation and first U.S. customer evaluations | One composition exceeds its matched G1/G4/G10 control on preregistered device and task metrics |
| P3 · Resilience and array proof, 30–48 months | G15–G21 F/Ca/Li studies, selector integration, small array, reliability and prototype module | US$7.0–18.0M | Dedicated tool modules where required, multi-mask runs, array circuits, U.S. package/test, radiation or cryogenic trials and application demonstrators | Reproducible selector-integrated task advantage, yield trend and transferable contamination plan |
| P4 · U.S. pilot transfer, 48–72 months | G19–G22 200 mm-compatible module, qualification lots, PDK/compact model, domestic second source and design wins | US$20–60M | U.S. foundry NRE, masks, qualification wafers, advanced packaging, reliability, process transfer, quality system and customer engineering | Quotation-backed good-die economics, qualification evidence and signed U.S. commercial pathway |
| Optional P5 · G24 consortium, 60–96 months | Separately qualified G9 optical, G23 spin and harvesting modules followed by U.S. heterogeneous integration | US$12–40M | Partner-funded transducers, photonic/spin test, known-good-die bonding, compound-yield learning and system validation | At least one module improves measured full-system function or energy–delay over the G21/G22 electrical baseline |
U.S. forecast totals: the staged G1–G22 core program is approximately US$31.1–87.7M over six years. Exercising the optional G24 consortium envelope produces an all-program planning range of approximately US$43.1–127.7M over eight years. These amounts are independent of, and must not be added to, CHIPS program totals or treated as awarded funding or project valuation.
Budget composition and forecast controls
| Cost pool | Indicative share by phase | Forecast driver | Control |
|---|---|---|---|
| Personnel and program delivery | 25–45% | Loaded FTE rate, hiring date, specialization and partner contribution | Named role plan, monthly burn and vacancy sensitivity |
| Facility, process and materials | 15–35% | Tool hours, minimum lot charge, targets/precursors, chamber dedication and consumables | Current quotations, purchase commitments and cost per completed learning cycle |
| Masks, wafers, circuits, test and packaging | 5–35% | Mask tier, wafer count, shuttle/full lot, die area, yield, package and test coverage | Release only after design review; compare quoted cost per good die |
| Metrology, reliability and external qualification | 10–25% | Sample count, instrument hours, beam/cryostat access and qualification matrix | Pre-register decision metric and stop duplicate low-value measurements |
| IP, EHS, quality, software and data | 5–12% | Jurisdictions, hazard controls, standards scope, licenses, compute and retention | Quarterly legal/EHS review and auditable data-cost allocation |
The USD forecast is re-baselined at every gate using actual burn, committed cost, U.S. supplier quotations, schedule risk and foreign-exchange exposure only for imported inputs. Report forecast-at-completion, estimate-to-complete, variance, peak cash need, runway and contingency draw in USD. Stress tests should apply at least a six-month schedule delay, a 10% increase in U.S. labor/facility rates, a 10% adverse move on imported inputs, one failed fabrication lot and the measured rather than target yield.
Gate 0 · AuthorizeRequirements, hypotheses, controls, risk and quotations approved
Gate 1 · LearnMinimum experiment resolves the highest-value uncertainty
Gate 2 · ReplicateIndependent run confirms effect size and failure bounds
Gate 3 · ScaleArray/system benefit and economic path justify the next capital step
Data and reproducibility plan
| Record | Minimum metadata | Control | Release rule |
|---|---|---|---|
| Sample and process | Unique ID, wafer coordinates, recipe/version, tool/chamber, precursor lots, operator, timestamps and deviations | Immutable raw log linked to LIMS or controlled repository | No plot without traceability to sample and recipe |
| Measurement | Instrument, calibration, wiring, environment, waveform, compliance, bandwidth and raw files | Read-only raw archive, checksum, open/non-proprietary export where possible | No summary value without raw waveform and analysis version |
| Analysis and simulation | Code commit, environment, parameters, seeds, exclusions and uncertainty model | Automated tests, review, container/lockfile and generated-result manifest | Figure must be reproducible from a tagged release |
| Statistics | Pre-registered endpoint, sample-size rationale, randomization, censoring and missing data | Device, cycle, wafer and run treated as distinct hierarchy levels | Report distributions/effect sizes and uncertainty, including negative results |
| Access and retention | Owner, sensitivity, license, embargo, retention period and disposal rule | Role-based access, backup verification and privacy/export review | Public FAIR package after IP/security review where permitted |
A7Claim Traceability & Glossary
Claim-to-source matrix
| Claim class | Current support | Permitted wording | Required upgrade |
|---|---|---|---|
| Ionic radii and 17.3% Sc/Ho mismatch | Calculation from Shannon six-coordinate radii; Reference 1 | Calculated reference-radius mismatch | Local coordination and strain from diffraction/spectroscopy or atomistic modelling |
| Ho₂S₃ existence/structure | Compound reference; Reference 2 | Known compound and candidate host | Phase-pure thin-film data for the actual process |
| VCM/ECM and memristive computing principles | General literature; References 3–5, 8–12 | Established mechanism/device families | Mechanism attribution in each proposed stack |
| Synaptic plasticity precedent | Published demonstrations in other devices; References 4, 6, 7 and 13 | Precedent for STP/LTP or neuromorphic operation | Matched local pulse and task demonstration |
| Unmeasured G1–G24 material performance | No local measurement dataset linked | Hypothesis, target, scenario or frontier concept | Versioned experiment/simulation with uncertainty and controls |
| Canadian supply availability | Project and capability statements in the supply section | Candidate source, project, operating capability, or R&D pathway as labelled | Supplier certificate, sample, specification, capacity, quotation and contract |
Every future quantitative claim receives a stable claim ID linked to a source type: LIT literature, CALC calculation, SIM simulation, EXP local experiment, SUP supplier evidence, or TGT design target. The dossier must display the source ID, revision and confidence next to the claim.
Glossary and notation
| Term | Definition used in this dossier |
|---|---|
| VCM | Valence-change mechanism: resistance modulation associated with anion defects, redox, interfaces or conductive regions; exact form is stack-dependent. |
| ECM / CBRAM | Electrochemical metallization / conductive-bridge RAM involving oxidation, ion transport and reduction of an active metal such as Ag or Cu. |
| STP / PPF | Short-term plasticity / paired-pulse facilitation: conductance or response changes that decay on a measured timescale. |
| LTP / LTD | Long-term potentiation / depression: retained increase/decrease of a synaptic weight under a declared retention criterion. |
| STDP | Spike-timing-dependent plasticity: update magnitude/sign depends on relative pulse timing; chemistry alone does not establish STDP. |
| 1T1R / 1S1R | One-transistor/one-resistor or one-selector/one-resistor cell used to control current and array addressing. |
| BEOL | Back end of line: post-transistor interconnect/process environment with product-specific thermal and contamination limits. |
| TRL / readiness gate | Evidence maturity, not performance rank. This dossier uses internal R0–R4 gates rather than claiming certified TRLs. |
| Forming-free | Specified switching behavior from the first qualified cycle without a separate higher-stress electroforming operation, reported statistically. |
| Effective bit depth | Number of statistically separable, usable conductance states under noise, drift, retention and read constraints; not pulse count. |
| Target | A design objective that has not been established as a measured property of the proposed stack. |
19Limitations & Open Questions
- The long-term co-existence of Ag⁺ and Li⁺ without cross-contamination must be demonstrated against the G16/G21 ≥10¹⁰-cycle endurance target; the G16 >10¹²-cycle value is an exploratory stretch target only.
- Li⁺ drift at the 450 K upper limit could narrow the retention window; accelerated tests will set the true derating curve.
- Tellurium is a scarce refining byproduct; aggregate multi-megawatt fleet or datacenter deployment, rather than one approximately 20 W chip, would require a validated material-intensity and recycling strategy.
- Sc³⁺/Ca²⁺ concentration homogeneity must be preserved through 3D vertical integration, where deposition conformality is harder.
- Separating the volatile (Ag⁺), intercalation (Li⁺), and vacancy (VCM) contributions requires more than I–V hysteresis — operando SIMS/TEM correlation is planned.
- Peripheral energy (ADCs, drivers) may dominate system power before the array does; the ~20 W chip target depends on the periphery roadmap.
Scientific blockers and realistic resolution paths
| Blocking question | Smallest decisive experiment | Realistic resolution | Fallback if the gate fails |
|---|---|---|---|
| Can the doped fluorosulfide be made as one controlled phase? | Composition-spread coupons across Sc/Ca/F content, followed by XRD, XPS, microscopy, stoichiometry and thermal cycling before electrical ranking. | Restrict the design to the measured single-phase or controlled-multiphase window; reduce dopant count rather than optimizing all variables together. | Return to G10 Ho₂S₃ or the G1 HfOx reference and retain the rejected dopant only as a separate interface experiment. |
| Can Ag, Li and host-defect state variables be separated? | Run Ag-only, Li-only, inert-electrode and paired G19 cells under equal delivered charge; use isotope/tracer depth profiles, coulometry and operando or interrupted spectroscopy. | Advance to one G21 cell only after each pathway has a distinct observable and predictive compact-model state. Screen an ion-selective or ion-blocking interlayer independently before integration. | Keep the physically separated G19 two-cell synapse, where fast and retained states remain independently addressable. |
| Does an Ag–Te reservoir meter Ag rather than undergo uncontrolled conversion? | Map reservoir phase and Ag chemical activity before/after bounded-charge pulses; quantify released Ag, residual Ag–Te stoichiometry and Te oxidation state. | Use the narrow phase/composition window with reproducible release, closed-loop charge compliance and a qualified diffusion barrier. | Use pure Ag or Cu with verify-write/current compliance, or metered metal nanoclusters, as the fast-path source. |
| Can mobile Ag/Li be confined from CMOS and neighboring cells? | SIMS/TEM depth profiles and electrical leakage after representative bias-temperature stress and BEOL-relevant anneals on barrier test structures. | Qualify redundant diffusion barriers and keep ionic processing in dedicated tools; bond a known-good ionic tile to conventional CMOS. | Keep the ionic device off the CMOS die and connect it as a replaceable package-level research module. |
| Can Li provide useful dynamics at cryogenic temperature? | Measure switching probability and extracted transport law versus pulse width and temperature from 300 K downward, with local thermometry to exclude Joule-heated activation. | Place Li programming at the warmest cryostat stage that meets latency and retention requirements; use cold-stage readout only. | At 4 K, use qualified Ag/VCM or cryo-CMOS state and treat the Li state as a warm-stage calibration memory. |
| Are 1,024 conductance levels actually distinguishable? | Blind program/read distributions across devices, cycles, retention times and temperatures, including ADC noise, drift and update asymmetry. | Use write-verify, calibration and error-aware training; specify effective bits from distribution overlap rather than pulse count. | Operate at the lower measured bit depth or encode one weight across multiple cells; do not preserve a nominal 10-bit claim. |
| Does 3D integration improve usable density and energy? | Compare one- and two-plane arrays with measured yield, vertical interconnect resistance, thermal coupling, sneak current and complete-task energy. | Stack only independently qualified planes and use redundancy around failed cells or vias. | Ship a planar or chiplet array if compound yield or cooling erases the geometric-density benefit. |
| Does the device save system energy after periphery? | Measure source-to-decision energy, latency and accuracy with drivers, selectors, ADC/DAC, calibration, communication, idle power and cooling included. | Reduce converter precision/rate, exploit event sparsity and keep analog accumulation local only where the workload benefits. | Use the device as nonvolatile calibration memory beside an MCU/NPU instead of as a full analog accelerator. |
20Relevant Companies, Universities & Research Infrastructure
Relationship boundaryThe organizations below are relevant because their public work intersects neuromorphic computing, in-memory computing, nanofabrication, packaging, quantum materials, or semiconductor commercialization. Inclusion identifies a potential benchmark, supplier, facility, research contact, or collaboration route; it does not claim endorsement, affiliation, access, funding, or an existing partnership with NEURO-SYNAPSE-OMNI.
Companies and industrial benchmarks
| Organization | Publicly documented relevance | NEURO-SYNAPSE-OMNI connection | Most relevant generations | Potential engagement | Boundary | Primary source |
|---|---|---|---|---|---|---|
| Intel Labs | Loihi 2, Lava, Kapoho Point, Hala Point, and the Intel Neuromorphic Research Community support event-driven spiking-system research. | Provides a digital neuromorphic baseline for temporal workloads, software mapping, system energy, latency, and scalability. | G1 system baseline; G4/G12/G19/G21 temporal tasks; G24 architecture comparison | Research-community participation, Lava workload port, matched benchmark, or independent system comparison. | Loihi performance does not validate the proposed materials; access and collaboration require Intel approval. | Intel Labs neuromorphic computing [14] |
| IBM Research | IBM publicly documents TrueNorth/NorthPole neuromorphic systems and research in brain-inspired and in-memory computing. | Offers architecture-level baselines for memory/compute colocation, digital precision, data movement, and complete-system benchmarking. | G1 baseline; G19–G24 system comparison | Literature benchmark, workload normalization, architecture review, or future joint evaluation. | IBM architectures use different devices and workloads; no direct material-performance equivalence is implied. | IBM neuromorphic overview [15] |
| Rain AI | U.S. company publicly focused on energy-efficient AI hardware and historically positioned around neuromorphic/in-memory concepts. | Relevant commercialization comparator for translating research hardware into accelerator prototypes, teams, and customer evidence. | G12–G22 commercialization | Comparable-company diligence, technical exchange, talent map, strategic investment discussion, or workload comparison. | Public material is limited; do not infer device stack, measured performance, partnership interest, or valuation. | Rain AI [16] |
| d-Matrix | Develops memory-centric digital in-memory compute and chiplet-based inference products. | Supplies a commercial digital baseline for latency, throughput, chiplet integration, software readiness, and total cost of inference. | G19–G24 product/system comparison | Benchmark specification, chiplet/package comparison, customer-requirement discovery, or ecosystem interoperability study. | Digital SRAM-based in-memory compute is not a direct memristor analogue; compare complete workloads and system cost. | d-Matrix technology [17] |
| EnCharge AI | Develops analog in-memory computing hardware and software for edge-to-cloud AI using an existing semiconductor supply chain. | Provides a high-value analog baseline for compute density, efficiency, robustness, software integration, and product qualification. | G5/G6/G12/G14/G16/G19/G21 | Matched analog-accuracy benchmark, commercialization comparison, process-risk review, or application-partner discovery. | Company performance claims remain configuration-specific and do not transfer to the proposed ionic stack. | EnCharge AI technology [18] |
| Prophesee | Commercializes event-based neuromorphic vision sensors and associated software. | Represents a natural event-camera input and customer workload for temporal filtering, sparse inference, and G9/G19/G21 in-sensor concepts. | G4, G9, G19, G21 and G24 | Dataset/workload integration, sensor-to-processor demonstrator, latency/energy benchmark, or application co-design. | An event sensor does not establish the benefit of a new memory; the combined system must beat a conventional event-processing baseline. | Prophesee event-based sensing [19] |
Worldwide semiconductor company map
Global ecosystem boundaryThe 24 companies below complement the strict 17-actor competitive register. They are potential foundry, equipment, metrology, memory, sensor, packaging, or industrial-reference organizations. Inclusion does not claim a partnership, technical acceptance, product fit, procurement route, capacity reservation, export authorization, or willingness to process Ho/S/Sc/Ag/Li/Te/F materials.
| Region | Company | Public industrial role | Potential OMNI relevance | Earliest credible engagement | Critical boundary |
|---|---|---|---|---|---|
| Taiwan | TSMC | Pure-play semiconductor foundry with advanced and specialty process platforms. | Long-term benchmark for PDK discipline, contamination rules, yield, reliability and process transfer. | Only after a qualified conventional bridge material, reproducible array data, contamination package and commercially credible volume case. | No TSMC compatibility or interest is implied; novel Ag/Li/Te/S/F chemistry may be excluded from production tools. |
| South Korea | Samsung Electronics · Device Solutions | Foundry, memory, logic, image-sensor and advanced-package semiconductor business. | Benchmark for memory integration, process control, heterogeneous systems and high-volume qualification. | Literature/process benchmark first; formal foundry review only after pilot-line evidence and a compatible integration split. | A broad semiconductor portfolio does not establish acceptance of the proposed materials or architecture. |
| United States | GlobalFoundries | Specialty foundry platforms for automotive, communications, IoT and differentiated technologies. | Potential future bridge for specialty-node control circuits, embedded integration or bonded companion die. | Conventional CMOS controller or chiplet discussion before any request involving novel ionic films. | Process availability, PDK access, wafer volumes, export controls and material acceptance require contract review. |
| Taiwan | UMC | Global pure-play foundry focused on mature and specialty process technologies. | Possible benchmark for cost-sensitive controller, selector or mixed-signal companion silicon. | Procure standard process capability through approved design channels; keep experimental chemistry off the foundry wafer initially. | No monolithic integration route is inferred from mature-node availability. |
| China | SMIC | Semiconductor foundry offering logic and specialty manufacturing platforms. | Global capacity and process-economics comparator for mature-node control/peripheral silicon. | Public benchmark and supply-chain scenario only unless legal, security, export and procurement reviews permit engagement. | Technology controls, jurisdiction, data/IP protection and customer eligibility can dominate technical fit. |
| Israel / global | Tower Semiconductor | Specialty analog, mixed-signal, sensor, power and RF foundry. | Potential controller, sensor-interface, high-voltage driver or readout companion die for G4–G9 modules. | Standard-platform feasibility and interface-chip design, followed by heterogeneous package integration. | Specialty capability does not imply acceptance of an experimental memory module. |
| Netherlands | ASML | Lithography systems, computational lithography and semiconductor manufacturing technology. | Roadmap reference for patterning, overlay, defectivity and scaling economics after large-cell chemistry is stable. | Use public patterning roadmaps and qualified shared-facility tools; direct tool engagement belongs to pilot/foundry partners. | ASML is not a fabrication service and lithography cannot solve unstable materials chemistry. |
| Netherlands | ASM International | Wafer-processing equipment for deposition, including atomic-layer and epitaxial technologies. | Reference for conformal barriers, interface control and eventual 3D layer uniformity. | Develop compatible barrier films on shared R&D tools before proposing production-equipment use. | Equipment capability does not establish a safe precursor, film process or chamber-contamination approval. |
| United States | Applied Materials | Materials-engineering equipment for deposition, modification, patterning and process integration. | Potential long-term process-equipment benchmark for reservoir, host, barrier and heterogeneous-integration modules. | Joint development only after coupon evidence defines target film, precursor/source, contamination and metrology specifications. | No tool compatibility or joint-development availability is implied. |
| United States | Lam Research | Deposition, etch, clean and wafer-fabrication equipment. | Reference for low-damage patterning, sidewall control, selective processing and 3D integration. | Qualify etch/clean on dedicated R&D coupons with residue and damage metrology. | Standard etch capability cannot be assumed for air-sensitive rare-earth sulfides or mobile-ion reservoirs. |
| Japan | Tokyo Electron | Coater/developer, deposition, etch, clean and test-related semiconductor equipment. | Global equipment benchmark for repeatable module integration and wafer-scale process control. | Partner-facility process development after chemistry and EHS envelopes are specified. | Listing does not imply tool access, chemistry approval, or support for experimental materials. |
| United States | KLA | Process control, inspection, metrology and yield-management systems. | Critical reference for film uniformity, defect maps, critical dimensions, contamination and yield learning. | Define measurable defect/yield signatures on pilot wafers before selecting production-class inspection methods. | Metrology detects variation but does not assign chemical mechanism without correlated analysis. |
| South Korea | SK hynix | Memory semiconductor and advanced-memory-system manufacturer. | Benchmark for memory reliability, test, packaging, high-volume yield and hierarchy economics. | Public memory benchmark and later strategic review only after OMNI demonstrates a differentiated array function. | Memory expertise does not imply interest in or compatibility with co-ionic materials. |
| United States | Micron Technology | Memory and storage semiconductor manufacturer. | Benchmark for endurance/retention definitions, test coverage, packaging, product lifecycle and cost per good bit. | Standards and published-product comparison before any licensing or joint-development discussion. | Conventional memory metrics must be normalized for analog synaptic operation and workload value. |
| Europe | STMicroelectronics | Integrated device manufacturer spanning MCUs, sensors, automotive, power and edge-AI products. | Potential application and companion-silicon benchmark for sensor-to-decision modules, automotive controls and packaging. | Demonstrate an evaluation module around standard MCU/sensor interfaces before proposing custom silicon integration. | No automotive, medical or industrial qualification follows from component availability. |
| Germany | Infineon Technologies | Automotive, industrial, power, security, sensor and embedded-control semiconductors. | Reference for robust mixed-signal control, functional safety, power management and harsh-environment qualification. | Use standard controllers and power devices in a demonstrator; pursue deeper integration only with measured application benefit. | Application relevance does not imply material acceptance or functional-safety readiness. |
| Germany | Bosch | Industrial and automotive technology company with sensors, MEMS and semiconductor research/manufacturing activities. | Potential workload/reference environment for vibration, acoustic, inertial and predictive-maintenance sensing. | Dataset or bounded sensor demonstrator before hardware qualification discussion. | Industrial use requires reliability, safety, cybersecurity and supply evidence beyond a laboratory cell. |
| Japan | Sony Semiconductor Solutions | Image-sensor and sensing semiconductor supplier. | Reference input ecosystem for G9 optical sensing and G24 heterogeneous vision concepts. | Interface a prototype to a commercially supported sensor before considering custom sensor-memory coupling. | Sensor leadership does not validate the OMNI memory or imply access to custom image-sensor processes. |
| Japan | Renesas Electronics | MCUs, MPUs, analog, power and embedded-AI semiconductor solutions. | Potential controller and evaluation-platform ecosystem for pulse generation, calibration, telemetry and edge workloads. | Build the first board around orderable standard components and documented interfaces. | A development-board ecosystem does not imply custom IP licensing or process integration. |
| France | Soitec | Engineered semiconductor substrates for RF, power, photonics and advanced electronics. | Long-term substrate and heterogeneous-integration reference for G9 optical and G23 spin modules. | Use standard substrates in separately optimized transducer demonstrators before requesting custom engineering. | An engineered substrate does not solve active-film phase, interface or transduction losses. |
| Taiwan | ASE Technology | Semiconductor assembly, test and advanced packaging services. | Potential long-term benchmark for chiplets, wafer-level packaging, thermal management, test and G24 heterogeneous tiles. | Package a conventional-controller plus experimental-die demonstrator after die-level yield and contamination controls exist. | OSAT engagement requires known-good-die, package rules, volume, liability and material-safety review. |
| United States / global | Amkor Technology | Outsourced semiconductor assembly, test and advanced-packaging provider. | Reference for package selection, thermal/mechanical simulation, qualification and scalable test. | Quotation-backed package feasibility after die dimensions, pads, thermal load and reliability mission are frozen. | No package route is available until experimental material handling and contamination are accepted. |
| China | JCET Group | Global semiconductor assembly, test and packaging services. | Alternative OSAT and cost/capacity benchmark for heterogeneous modules. | Supply-chain scenario and legal/procurement review before any technical engagement. | Jurisdiction, export control, IP/data protection and customer requirements may preclude a route. |
| India | Tata Electronics | Growing electronics and semiconductor manufacturing, assembly and packaging ecosystem. | Long-horizon geographic diversification and scale-up comparator for packaging/manufacturing strategy. | Monitor qualified capabilities and customer-access models as they become operational and relevant. | Announced capacity or construction is not equivalent to an available qualified process for OMNI. |
How to use the global mapChoose a company by the uncertainty it can close, not by brand size. Early G1–G14 work needs flexible shared R&D tools and chemical analysis; G19–G22 needs selector, packaging and pilot-yield partners; G23–G24 needs separately qualified sensor, photonic, spin and bonding modules. Major production foundries become relevant only after those gates.
Universities, public laboratories, and prototyping infrastructure
| Organization | Publicly documented capability | NEURO-SYNAPSE-OMNI contribution | Most relevant work package | Potential engagement | Boundary | Primary source |
|---|---|---|---|---|---|---|
| Purdue University · C-BRIC | Center for Brain-Inspired Computing spanning neuro-inspired algorithms, neuromorphic fabrics, distributed intelligence, and application drivers. | Algorithm–device co-design, temporal workloads, accelerator baselines, autonomous-system use cases, and independent task metrics. | G4/G9/G12/G19/G21/G24 workload definition and system proof | Sponsored research, benchmark design, student project, architecture review, or multi-university proposal. | The cited C-BRIC program establishes domain relevance, not current availability or project participation. | Purdue C-BRIC [20] |
| MIT · MIT.nano | Shared nanofabrication and characterization facilities covering lithography, deposition, etching, wet processing, and nanoscale metrology. | Potential access model for thin-film coupons, device patterning, microscopy, process learning, and training. | G1–G21 materials/device fabrication | External-user application, sponsored project, facility quotation, or specialist characterization. | Tool compatibility with Ho/S/Sc/Ag/Li/Te/F chemistry must be approved before any process is proposed. | MIT.nano facilities [21] |
| Université de Sherbrooke · Institut quantique | Research institute with quantum-material, device, cryogenic, and technological-platform activities. | Relevant to 4 K transport, low-noise measurement, quantum-material interfaces, Bi₂Te₃/Er questions, and realistic cryogenic heat-load tests. | G19/G21 cryogenic qualification and G23/G24 component research | Joint grant, platform-access inquiry, graduate research, cryogenic measurement campaign, or materials collaboration. | Quantum expertise does not imply that the proposed ionic device operates at 4 K or is compatible with qubits. | Institut quantique research [22] |
| C2MI · Bromont | Canadian R&D and commercialization infrastructure for MEMS, advanced packaging, compound semiconductors, electronic systems, and prototyping. | Potential bridge from coupon/device research to packaging, heterogeneous integration, reliability, pilot transfer, and customer demonstrators. | G19–G22 pilot transfer and G24 heterogeneous tile | Feasibility review, quotation-backed package/test plan, prototype run, contamination assessment, or industrial consortium. | C2MI listing does not establish process acceptance; every material, tool, IP, cost, and schedule term requires formal review. | C2MI capabilities [23] |
| Sandia National Laboratories | Hosts Intel Hala Point for research spanning device physics, computer architecture, computer science, and informatics. | Represents a public-laboratory benchmark environment for large-scale neuromorphic workloads, mission relevance, and scientific computing. | G15 harsh-environment use cases; G19/G21/G24 system benchmarking | Future open call, funded collaboration, mission-workload definition, or independent benchmarking subject to eligibility. | Deployment of Hala Point at Sandia does not imply access, endorsement, procurement, or interest in this project. | Intel/Sandia Hala Point announcement [24] |
| NIST / CHIPS for America | U.S. semiconductor R&D, metrology, manufacturing-incentive, NSTC, and advanced-packaging programs. | Relevant to standards, measurement traceability, prototyping ecosystems, packaging roadmaps, and U.S. scale-up pathways. | All generations; strongest from G19 pilot transfer onward | Monitor calls, join eligible ecosystem activities, align metrology, or apply through a qualified U.S. consortium. | Program totals are not available project funding; eligibility, cost share, scope, and award terms control access. | NIST CHIPS for America [25] |
Engagement sequence
1 · BenchmarkUse Intel, IBM, d-Matrix, EnCharge AI, and Prophesee public systems to define workloads and complete-system baselines
2 · ResearchApproach domain-matched university groups only with a bounded hypothesis, funded work package, controls, and publication/IP terms
3 · FabricateRequest facility compatibility and quotations before naming MIT.nano, C2MI, or another shared facility in a committed process route
4 · QualifyUse NIST-traceable methods, independent replication, package/reliability partners, and customer-defined acceptance gates
5 · ContractConvert interest into NDA, statement of work, IP schedule, milestones, budget, data rights, and explicit no-endorsement language
Recommended first outreach: pursue one algorithm/workload university, one materials/device facility, one packaging/pilot organization, and one customer-facing compute company in parallel. The first request should be a paid, bounded feasibility package rather than an open-ended partnership proposal.
21Background References
- R. D. Shannon, “Revised effective ionic radii and systematic studies of interatomic distances in halides and chalcogenides,” Acta Crystallographica A 32, 751–767 (1976). doi:10.1107/S0567739476001551
- Landolt-Börnstein, “Ho₂S₃: crystal structure, physical properties,” Non-Tetrahedrally Bonded Binary Compounds II. doi:10.1007/10681735_623
- R. Waser and M. Aono, “Nanoionics-based resistive switching memories,” Nature Materials 6, 833–840 (2007). doi:10.1038/nmat2023
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22Frequently Asked Questions
Fourteen questions are answered below in accessible HTML disclosure controls.
Why investigate two cations (Ag⁺ and Li⁺)?
The design assigns a potentially fast, volatile pathway to Ag⁺ and a potentially slower, distributed insertion pathway to Li⁺. Their separation, interaction, retention, and 1,024-level target must all be measured in the complete stack.
Does a vacancy have a physical size or atomic mass?
Not in the same sense as an ion. A vacancy is an unoccupied crystallographic site. The quoted 1.40 Å and 1.84 Å values describe six-coordinate O²⁻ and S²⁻ reference radii, while 16.00 u and 32.06 u describe atomic masses. Vacancy motion depends on the surrounding lattice and energy landscape.
Are sulfur vacancies automatically faster than oxygen vacancies?
No. Migration depends on the host phase, pathway geometry, local bonding, defect charge, dopants, interfaces, field, and temperature. A softer sulfide lattice may lower a barrier despite the larger sulfur ion, but Ho₂S₃ and Ho₂S₃:Sc require direct DFT/NEB and temperature-dependent measurements.
Are oxide memristors only digital and sulfide memristors always analog?
No. Both material families can show abrupt binary or gradual multilevel switching. Current compliance, pulse amplitude and width, feedback, film thickness, interfaces, and filament morphology often determine the operating regime as strongly as anion chemistry.
How can VCM be separated from Ag or Cu ECM?
Compare inert-electrode Pt/Pt or Au/Pt cells with matched Ag/Pt and Cu/Pt cells, then correlate electrical states with SIMS, XPS, TEM/EDS, or operando measurements. A change seen only with an active metal supports ECM; persistence with inert electrodes supports a host or interface mechanism.
What environmental risk is specific to sulfide films?
Sulfur loss, surface oxidation toward oxysulfides or oxides, and moisture-dependent reactions can alter stoichiometry and switching. Encapsulated and unencapsulated films should be compared under controlled humidity, oxygen, temperature, and storage time.
Has Ho₂S₃:Sc resistive switching been demonstrated?
Not by the references currently assembled in this dossier. Ho₂S₃ is a known compound and the Sc/Ho radius mismatch is calculable, but the proposed vacancy control, analog switching, endurance, voltage, and retention remain hypotheses requiring fabricated control series.
How could calcium make the device forming-free?
Ca²⁺ is aliovalent on Ho³⁺ sites. In the stated fixed-valence substitution/vacancy model, compensation by F⁻ substitution and/or sulfur vacancies gives y = z + 2δ; spectroscopy and defect calculations must test for mixed valence, interstitials, carriers, or other compensation. Controls must then show whether the resulting defects eliminate electroforming and permit the 0.2 V target.
What exactly could scandium do?
Its six-coordinate reference radius has a 17.3% Ho-referenced mismatch, so substitution may alter local strain and defect energetics. DFT, microscopy, and hierarchical switching statistics must test whether this biases a repeatable path; ordered rails and separate CVC2C(VSET) and CVD2D(VSET) < 2% have not yet been demonstrated.
Does scandium necessarily widen the bandgap?
No. Ho 4f, Sc 3d, and S 3p hybridization can change the density of states, but neither the sign nor magnitude follows from orbital labels alone. No numerical bracket is retained without a phase- and composition-matched source; optical spectroscopy and electronic-structure calculations are required.
How should ten-year high-temperature retention be established?
Measure HRS and LRS drift at several elevated temperatures, fit a physically justified Arrhenius model, disclose the activation energy and confidence interval, and verify that no phase or interface change invalidates the extrapolation.
Does lithium tunnelling guarantee operation at 4 K?
No. Low lithium mass can favour quantum effects, but simple-barrier tunnelling probability decreases approximately exponentially with barrier width and with the square root of barrier height; attempt frequency, field, available sites, lattice coupling and dissipation also affect the rate. The 4 K figure is a test target, not a measured property.
Is tellurium a CMOS contamination risk?
Potential Ag–Te or Li–Te phase formation may change chemical activity and diffusion, but the direction and magnitude are composition- and process-dependent. SIMS depth profiling, phase analysis, barrier tests, and anneals must quantify Ag/Li/Te migration before any BEOL-compatibility claim.
Is the supply chain really 100% Canadian?
Not yet as a qualified manufacturing chain. Canadian resources or projects exist for the principal elements, but device-grade refining, precursor conversion, deposition targets, production capacity, contracts, and packaging must all be demonstrated. Sorel-Tracy scandium from titanium-process residues is an active circular route; Crater Lake is a development project; scandium recovery from Vaudreuil bauxite residue remains an R&D opportunity.
23Roadmap 2026 – 2035+
2026
G1–G4 · Electrical referencesQualify oxide VCM plus independent Cu and Ag ECM controls.2027–2028
G5–G9 · Tuning and accessDown-select Cr/Mn, selectors and the optical input module using matched controls.2028–2031
G10–G14 · Host and reservoirsEstablish the sulfide host, barriers, Ag/Cu reservoirs and Sc causality.2030–2034
G15–G19 · Ionic functionsQualify passivation, compensation, Li insertion and the paired fast/slow architecture.2033–2038
G20–G22 · Frontier cells and 3DBound Au risk, prove co-ionic attribution, then stack only the selected cell.2037–2040+
G23–G24 · Heterogeneous systemQualify spin and optical links separately before complete OMNI integration.24Conclusion
NEURO-SYNAPSE-OMNI does not ask one ion to do everything. The architecture investigates silver for volatility, lithium for retained insertion, scandium for filament bias, calcium for defect control, and fluorine for passivation — all inside a holmium fluorosulfide host. These assignments convert known memristor limitations into experimentally separable design variables rather than presuming that each target has already been achieved.
The next milestone is statistical: a controlled comparison of reservoir compositions and dopant levels, reported as full distributions. The 10-bit, 0.2 V, 4 K, 450 K, and radiation-tolerance objectives remain targets unless supported by reproducible measurements and application-specific qualification.