Revolutionary ternary logic architecture {-1, 0, +1} on a topological Bi2Se3 layer, with a native ternary instruction set (T-ISA) and integrated memristor memory.
A fundamental breakthrough in digital computing
Unlike binary limited to 2 states, ternary logic encodes 3 states per trit. A register of n trits stores 3n values versus 2n in binary - that is log2(3)/log2(2) - 1.585x more information per state unit.
Bismuth selenide (Bi2Se3) is a topological insulator: insulating in bulk but conducting on the surface via protected edge states. Low contact resistance, thermal stability up to 270 C, quantum spin Hall effect.
| Parameter | Binary | Ternary Bismuth |
|---|---|---|
| States per digit | 2 (0, 1) | 3 (-1, 0, +1) |
| Info per state | 1 bit | 1.585 bits |
| Logic gates | AND, OR, NOT | MIN, MAX, INV, NAND3 |
| Power consumption | 1x (reference) | 0.67x estimated |
| Die area | 1x (reference) | 0.73x estimated |
A complete set of hardware-wired gates operating on {-1, 0, +1} states
Inputs on columns / rows; color = output state (-1 purple, 0 gray, +1 gold)
Non-volatile ternary on-die RAM
Memristors exploit 3 distinct resistance levels (R_low, R_mid, R_high) to natively encode trits {-1, 0, +1}. Integrated directly on-die next to compute cores, they eliminate the classic memory bottleneck.
TVX - TPU - GPU - NPU - APU - VPU - ISP - SEC - DSP
Why a triangular die instead of a square one - a full analysis of heat dissipation and its trade-offs
The ternary audio/signal processing unit embeds a broad range of DSP functions wired in hardware, leveraging 3-state resolution for extended dynamic range and low latency.
Every technology of the latest market processors, reimagined in ternary
Native {-1, 0, +1} machine instructions wired on-die to maximize ternary compute strength
Compact encoding: each instruction fits in 2 trytes (6 trits) - ~9.5 equivalent binary bits - giving ~40% higher code density vs binary.
Quadratic - Trigonometry - Complex Numbers - Maths & Physics
Select an equation to visualize its dedicated animation
Hardware acceleration across every domain of numerical computing
Hardware acceleration across the major fields of physics
Biological units that push the processor beyond its limits
Ternary logic {-1, 0, +1} naturally mirrors biological processes (inhibition / rest / excitation). Ternium embeds bio-inspired co-processors that accelerate genomics, molecular simulation and organic neural networks.
Each DNA base maps onto trit states for native genomic processing
Click the bases to build a sequence and watch it encode into trits in real time
Living signals have three states - exactly like {-1, 0, +1} logic
The membrane potential crosses two thresholds: below the inhibitory threshold it encodes -1, at rest 0, above the excitatory threshold +1. A single ternary neuron thus replaces two binary neurons.
How the processor's functions are wired at the transistor level
Ternary logic relies on multi-threshold transistors (MVT). By combining MOSFETs with low and high threshold voltages, each gate produces three output levels: 0 V for -1, V_dd/2 for 0, and V_dd for +1. Select an input level to see which transistors conduct.
Two PMOS (pull-up) and two NMOS (pull-down) with shifted thresholds invert the three levels: -1 to +1, 0 to 0, +1 to -1.
Input level
Output +1 - V_ddTERN-GCC and 12-stage pipeline architecture
| Cache | Size | Latency | Position |
|---|
From the silicon-bismuth wafer to the finished ternary processor - step by step
Every Ternium product follows these 8 steps, tuned to its target
Ternium T1 vs Binary Silicon
From prototype to production
Claims in this document combine established semiconductor engineering with forward-looking architecture projections.
Core ternary logic mathematics, known fabrication steps, and baseline performance-model methodology.
Projected architecture-level efficiency and density benefits under constrained implementation assumptions.
Industrial-scale adoption timelines and ecosystem migration across full software/hardware stacks.
Reference families include ternary computing literature, ISA/compiler optimization sources, memristor research, and process/fabrication engineering documents.